View ELANSC520-100AC_6870659.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary ? copyright 2001 advanced micro devices, inc. all rights reserved. final draft# 22003 rev: b amendment/ 0 issue date: march 2001 lan?sc520 microcontroller integrated 32-bit microcontroller with pc/at-compatible peripherals, pci host bridge, and synchronous dram controller distinctive characteristics n industry-standard am5 x 86? cpu with floating point unit (fpu) and 16-kbyte write-back cache C 100-mhz and 133-mhz operating frequencies C low-voltage operation (core v cc = 2.5 v) C 5-v tolerant i/o (3.3-v output levels) n e86? family of x86 embedded processors C part of a software-compatible family of microprocessors and microcontrollers well supported by a wide variety of development tools n integrated pci host bridge controller leverages standard peripherals and software C 33 mhz, 32-bit pci bus revision 2.2-compliant C high-throughput 132-mbyte/s peak transfer C supports up to five external pci masters C integrated write-posting and read-buffering for high-throughput applications n synchronous dram (sdram) controller C supports 16-, 64-, 128-, and 256-mbit sdram C supports 4 banks for a total of 256 mbytes C error correction code provides system reliability C buffers improve read and write performance n amdebug ? technology offers a low-cost solution for the advanced debugging capabilities required by embedded designers C allows instruction tracing during execution from the am5 x 86 cpus internal cache C uses an enhanced jtag port for low-cost debugging C parallel debug port for high-speed data exchange during in-circuit emulation n general-purpose (gp) bus with programmable timing for 8- and 16-bit devices provides good performance at low cost n rom/flash controller for 8-, 16-, and 32-bit devices n enhanced pc/at-compatible peripherals provide improved performance C enhanced programmable interrupt controller (pic) prioritizes 22 interrupt levels (up to 15 external sources) with flexible routing C enhanced dma controller includes double buffer chaining, extended address and transfer counts, and flexible channel routing C two 16550-compatible uarts operate at baud rates up to 1.15 mbit/s with optional dma interface n standard pc/at-compatible peripherals C programmable interval timer (pit) C real-time clock (rtc) with battery backup capability and 114 bytes of ram n additional integrated peripherals C three general-purpose 16-bit timers provide flexible cascading for 32-bit operation C watchdog timer guards against runaway software C software timer C synchronous serial interface (ssi) offers full-duplex or half-duplex operation C flexible address decoding for programmable memory and i/o mapping and system addressing configuration n 32 programmable input/output (pio) pins n native support for psos, qnx, rtxc, vxworks, and windows ? ce operating systems n industry-standard bios support n plastic ball grid array (pbga388) package general description the lan?sc520 microcontroller is a full-featured mi- crocontroller developed for the general embedded market. the lansc520 microcontroller combines a 32-bit, low-voltage am5 x 86 cpu with a set of inte- grated peripherals suitable for both real-time and pc/ at-compatible embedded applications. an integrated pci host bridge, sdram controller, enhanced pc/at-compatible peripherals, and advanced debugging features provide the system designer with a wide range of on-chip resources, allowing support for legacy devices as well as new devices available in the current pc marketplace. designed for medium- to high-performance applications in the telecommunications, data communications, and information appliance markets, the lansc520 micro- controller is particularly well suited for applications re- quiring high throughput combined with low latency. the compact plastic ball grid array (pbga) package pro- vides a high degree of functionality in a very small form factor, making it cost-effective for many applications. a 0.25-micron cmos manufacturing process allows for low power consumption along with high performance.
2 lan?sc520 microcontroller data sheet preliminary ordering information C100 = 100 mhz C133 = 133 mhz temperature range speed option device number/description valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. valid combinations package type a = 388-pin plastic ball grid array (pbga) lansc520 integrated 32-bit microcontroller with pc/at-compatible peripherals, pci host bridge, and synchronous dram controller C133 a c valid combinations lansc520C100 lansc520C133 ac lansc520 c= commercial (t c =0 ? c to +85 ? c) where: t c = case temperature
preliminary lan?sc520 microcontroller data sheet 3 table of contents distinctive characteristics ................................................................................................... ......... 1 general description ........................................................................................................... .......... 1 ordering information .......................................................................................................... .......... 2 logic diagram by interface ..................................................................................................... ...... 6 logic diagram by default pin function ........................................................................................ 7 connection diagram ............................................................................................................ ........ 8 pin designations .............................................................................................................. .......... 10 pin designations (pin number) ............................................................................................. 11 pin designations (pin name) ................................................................................................ 13 signal descriptions ........................................................................................................... .......... 16 architectural overview ........................................................................................................ ....... 28 industry-standard x86 architecture ....................................................................................... 30 amdebug? technology for advanced debugging .............................................................. 30 industry-standard pci bus interface .................................................................................... 30 high-performance sdram controller ................................................................................. 30 rom/flash controller .......................................................................................................... .30 flexible address-mapping hardware .................................................................................... 31 easy-to-use gp bus interface .............................................................................................. 31 clock generation .............................................................................................................. .... 31 integrated peripherals ........................................................................................................ ... 31 jtag boundary scan test interface .................................................................................... 32 system test and debug features ........................................................................................ 32 applications .................................................................................................................. ............. 33 clock generation and control .................................................................................................. .38 internal clocks ............................................................................................................... ....... 39 clock specifications .......................................................................................................... .... 40 clock pin loading ............................................................................................................. .... 40 selecting a crystal ........................................................................................................... ..... 41 32.768-khz crystal selection ........................................................................................... 41 33-mhz crystal selection................................................................................................. 42 third overtone crystal component selection.................................................................. 42 running the lan?sc520 microcontroller at 33.333 mhz ........................................................... 43 bypassing internal oscillators ............................................................................................... 4 4 rtc voltage monitor ........................................................................................................... ...... 45 backup battery considerations ............................................................................................. 46 using an external rtc backup battery ........................................................................... 46 not using an external rtc backup battery..................................................................... 46 absolute maximum ratings ...................................................................................................... .48 operating ranges at commercial temperatures ...................................................................... 48 voltage levels for non-pci interface pins ................................................................................ 49 voltage levels for pci interface pins ........................................................................................ 4 9 dc characteristics over commercial operating ranges .......................................................... 50 capacitance ................................................................................................................... ............ 51 non-pci interface pin capacitance ...................................................................................... 51 pci interface pin capacitance .............................................................................................. 51 crystal capacitance ........................................................................................................... ... 51 derating curves ............................................................................................................... ..... 51 power characteristics ......................................................................................................... ....... 56 thermal characteristics ....................................................................................................... ............56 388-pin pbga package .......................................................................................................... ...56 switching characteristics and waveforms ................................................................................ 58 key to switching waveforms ................................................................................................ 58
4 lan?sc520 microcontroller data sheet preliminary ac switching test waveforms .................................................................................................. 5 8 non-pci bus interface pins .................................................................................................. 58 pci bus interface pins ........................................................................................................ .. 58 switching characteristics over commercial operating ranges .................................................................... 59 power-on reset timing ........................................................................................................ 5 9 reset timing with power applied ......................................................................................... 61 rom timing .................................................................................................................... ...... 63 pci bus timing ................................................................................................................ ..... 65 sdram timing .................................................................................................................. ... 66 sdram clock timing ........................................................................................................... 6 8 gp bus timing ................................................................................................................. ..... 69 gp bus dma read cycle timing ......................................................................................... 71 gp bus dma write cycle timing .......................................................................................... 72 ssi timing .................................................................................................................... ......... 73 jtag timing ................................................................................................................... ...... 74 appendix a: pin tables ........................................................................................................ ....a-1 pin list summary table column definitions ............................................................................ a-6 appendix b: physical dimensions ............................................................................................b-1 388-pin plastic bga (pbga) package ................................................................................b-1 top view ...................................................................................................................... ........b-1 bottom view .................................................................................................................. ......b-2 circuit board layout considerations ....................................................................................b-3 appendix c: customer support ................................................................................................c- 1 related documents ............................................................................................................. .c-2 additional information ........................................................................................................ ..c-2 customer development platform .........................................................................................c-2 third-party development support products .................................................................................c-2 customer service .............................................................................................................. ...c-3 hotline and world wide web support............................................................................. c-3 corporate applications hotline........................................................................................ c-3 world wide web home page ......................................................................................... c-3 documentation and literature ......................................................................................... c-3 literature ordering .......................................................................................................... c -3 index .......................................................................................................................... ......... index-1 list of figures figure 1. lan?sc520 microcontroller block diagram ....................................................... 29 figure 2. lan?sc520 microcontroller-based smart residential gateway reference design ................................................................................................. 34 figure 3. lan?sc520 microcontroller-based thin client reference design .................... 35 figure 4. lan?sc520 microcontroller-based digital set top box reference design ....... 36 figure 5. lan?sc520 microcontroller-based telephone line concentrator reference design ................................................................................................. 37 figure 6. system clock distribution block diagram ............................................................. 38 figure 7. clock source block diagram ................................................................................ 39 figure 8. 32.768-khz crystal circuit .................................................................................... 41 figure 9. 33.333-mhz third overtone crystal implementation ............................................ 43 figure 10. bypassing the 32.768-khz oscillator .................................................................... 44 figure 11. bypassing the 33-mhz oscillator .......................................................................... 44 figure 12. rtc voltage monitor block diagram .................................................................... 45 figure 13. circuit with backup battery ................................................................................... 47 figure 14. circuit without backup battery .............................................................................. 47 figure 15. i/o drive 6-ma rise time ..................................................................................... 52
preliminary lan?sc520 microcontroller data sheet 5 figure 16. i/o drive 6-ma fall time ....................................................................................... 52 figure 17. i/o drive 12-ma rise time ................................................................................... 53 figure 18. i/o drive 12-ma fall time ..................................................................................... 53 figure 19. i/o drive 24-ma rise time ................................................................................... 54 figure 20. i/o drive 24-ma fall time ..................................................................................... 54 figure 21. pci pads rise time with 1-ns rise/fall ............................................................... 55 figure 22. pci pads fall time with 1-ns rise/fall ................................................................. 55 figure 23. thermal resistance ( ? c/watt) .............................................................................. 56 figure 24. thermal characteristics equations ....................................................................... 57 figure 25. ac switching test waveforms .............................................................................. 58 figure 26. power-up timing sequence ................................................................................. 60 figure 27. pwrgood timing for rtc standalone mode .................................................... 60 figure 28. external system reset timing with power applied .............................................. 61 figure 29. prgreset timing ............................................................................................... 62 figure 30. internal system reset timing ............................................................................... 62 figure 31. non-burst rom read cycle timing ..................................................................... 64 figure 32. page-mode rom read cycle timing ................................................................... 64 figure 33. flash write cycle timing ...................................................................................... 65 figure 34. sdram write and read timing ........................................................................... 67 figure 35. sdram clock timing ........................................................................................... 68 figure 36. gp bus non-dma cycle timing ........................................................................... 70 figure 37. gp-dma read cycle timing ................................................................................ 71 figure 38. gp-dma write cycle timing ................................................................................. 72 figure 39. ssi timing .......................................................................................................... ... 73 figure 40. jtag boundary scan timing ................................................................................ 74 figure 41. bga ball pad layout ...........................................................................................b-3 list of tables table 1. signal descriptions table definitions..................................................................... 16 table 2. signal descriptions ............................................................................................... 17 table 3. clock jitter specifications ..................................................................................... 40 table 4. clock startup and lock times .............................................................................. 40 table 5. oscillator input specifications ............................................................................... 40 table 6. analog vcc (vcc_anlg) specifications ............................................................ 40 table 7. pll1 loop filter components .............................................................................. 41 table 8. timing error as it translates to clock accuracy .................................................... 41 table 9. 32.768-khz crystal specifications ........................................................................ 42 table 10. 33-mhz crystal specifications .............................................................................. 42 table 11. rtc voltage monitor component specifications .................................................. 46 table 12. device power dissipation ..................................................................................... 56 table 13. vcc_anlg and vcc_rtc power dissipation .................................................... 56 table 14. thermal resistance (c/w) q jc and q ja for bga package with 6-layer board ... 57 table 15. maximum t a for plastic bga package with 6-layer board with t case = 85c .... 57 table 16. multiplexed signal trade-offs ..............................................................................a-2 table 17. pios sorted by pio number ................................................................................a-4 table 18. pios sorted by signal name ...............................................................................a-5 table 19. pin list summary table abbreviations .................................................................a-6 table 20. pin list summary .................................................................................................a-7 table 21. related amd productse86? family devices ..................................................c-1
6 lan?sc520 microcontroller data sheet preliminary logic diagram by interface 1 notes: 1. pins noted with asterisks are duplicated in this diagram to clarify which signals are used for each interface. pci bus sdram serial ports: uart 1 uart 2 ssi ad31Cad0 cbe3 Ccbe0 pa r serr perr frame trdy irdy stop devsel clkpciout clkpciin rst inta Cintd req4 Creq0 gnt4 Cgnt0 ba1Cba0 md31Cmd0 scs3 Cscs0 clkmemout clkmemin srasa Csrasb scasa Cscasb swea Csweb sdqm3Csdqm0 mecc6Cmecc0 sout2Csout1 sin2Csin1 rts2 Crts1 cts2 Ccts1 dsr2 Cdsr1 dtr2 Cdtr1 dcd2 Cdcd1 rin2 Crin1 ssi_clk ssi_do ssi_di gp bus gpa25Cgpa0 gpd15Cgpd0 gpreset gpiord gpiowr gpmemrd gpmemwr gpale gpbhe gprdy gpaen gptc gpdrq3Cgpdrq0 gpdack3 Cgpdack0 gpirq10Cgpirq0 gpdbufoe gpiocs16 gpmemcs16 jtag amdebug system test jtag_trst jtag_tck jtag_tdi jtag_tdo jtag_tms gpcs7 Cgpcs0 bootcs romcs2 Cromcs1 romrd flashwr rombufoe cmdack br/tc stop/tx trig/trace wbmstr2Cwbmstr0 cf_dram datastrb cf_rom_gpcs pio31Cpio0 tmrin1Ctmrin0 tmrout1Ctmrout0 programmable input/output timers pitgate2 pitout2 clocks and reset 32kxtal2C32kxtal1 33mxtal2C33mxtal1 clktimer clktest pwrgood prgreset cfg3Ccfg0 rstld7Crstld0 configuration debug_enter inst_trce amdebug_dis bbatsen md31Cmd0* gpa25Cgpa0* gpd15Cgpd0* rom/flash ma12Cma0 lf_pll1
lan?sc520 microcontroller data sheet 7 preliminary logic diagram by default pin function 1 notes: 1. pin names in bold indicate the default pin function. brackets, [ ], indicate alternate, multiplexed functions. braces, { }, indicate pinstrap pins. pins noted with asterisks are duplicated in this diagram to clarify which signals are used for each interface. pci bus sdram serial ports: uart 1 uart 2 ssi ad31Cad0 cbe3 Ccbe0 pa r serr perr frame trdy irdy stop devsel clkpciout clkpciin rst inta Cintd req4 Creq0 gnt4 Cgnt0 ba1Cba0 md31Cmd0 scs3 Cscs0 clkmemout clkmemin srasa Csrasb scasa Cscasb swea Csweb sdqm3Csdqm0 mecc6Cmecc0 sout2Csout1 sin2Csin1 rts2 Crts1 cts1 dsr1 dtr2 Cdtr1 dcd1 rin1 ssi_clk ssi_do ssi_di gp bus rom/flash gpa25 {debug_enter} gpd15Cgpd0 gpreset gpiord gpiowr gpmemrd gpmemwr pio0 [gpale] pio1 [gpbhe ] pio2 [gprdy] pio3 [gpaen] pio4 [gptc] pio5Cpio8 [gpdrq3Cgpdrq0] pio9Cpio12 [gpdack3 Cgpdack0 ] pio13Cpio23 [gpirq10Cgpirq0 ] pio24 [gpdbufoe ] pio25 [gpiocs16 ] pio26 [gpmemcs16 ] jtag amdebug system test jtag_trst jtag_tck jtag_tdi jtag_tdo jtag_tms pio27 [gpcs0 ] bootcs romcs2 Cromcs1 [gpcs2 Cgpcs1 ] romrd flashwr rombufoe cmdack br/tc stop/tx trig/trace cf_dram [wbmstr2] {cfg2} datastrb [wbmstr1] {cfg1} cf_rom_gpcs [wbmstr0] {cfg0} tmrin1Ctmrin0 [gpcs4 Cgpcs5 ] tmrout1Ctmrout0 [gpcs6 Cgpcs7 ] timers pitgate2 [gpcs3 ] pitout2 {cfg3} clocks and reset 32mxtal2C32mxtal1 lf_pll1 clktimer [clktest] pwrgood prgreset bbatsen gpa22Cgpa15 {rstld7Crstld0} gpa13Cgpa0 gpa24 {inst_trce} gpa23 {amdebug_dis} pio28 [cts2 ] pio29 [dsr2 ] pio30 [dcd2 ] pio31 [rin2 ] md31Cmd0* gpa25Cgpa0* gpd15Cgpd0* ma12Cma0 32kxtal2C32kxtal1
8 lan?sc520 microcontroller data sheet preliminary connection diagram 388-pin plastic bga package top view 12345678910111213 a ad30 ad31 nc clkmemin rst clk- pciout clktimer [clktest] md1 md17 md3 md19 md5 md21 a b ad29 ad28 nc nc gpd1 nc md0 md16 md2 md18 md4 md20 md6 b c gpa6 gpa9 gpa25 {debug_ enter} gpd0 nc nc gpd2 gpd3 gpd4 gpd7 gpd8 gpd9 gpd10 c d ad26 ad27 gpa23 {amdebug _dis} gpa24 {i n s t _trce} v c c _ i / o v c c _ i / o v c c _ i / o v c c _ i / o g p d 5 g p d 6 vcc_core vcc_core g p d 1 1 d e a d 2 5 a d 2 4 n c vcc_core e f ad23 cbe3 gpa22 {rstld7} vcc_core f g ad22 ad21 clkpciin gpa1 g h ad19 ad20 intc intd h j ad18 ad17 intb vcc_i/o j k cbe2 ad16 inta vcc_i/o k l frame irdy req0 vcc_i/o gnd gnd gnd l m devsel trdy gnt0 vcc_i/o gnd gnd gnd m n stop perr req1 gnt1 gnd gnd gnd n p pa r s e r r gnt2 req2 gnd gnd gnd p r cbe1 ad15 req3 vcc_core gnd gnd gnd r t ad13 ad14 gnt3 vcc_core gnd gnd gnd t u ad12 ad11 req4 gnt4 u v ad9 ad10 cts1 dcd1 v w ad8 cbe0 dtr1 rts1 w y ad6 ad7 dsr1 vcc_i/o y aa ad5 ad4 rin1 vcc_i/o aa ab ad2 ad3 nc nc ab ac ad1 ad0 nc pio25 [gpiocs16 ] vcc_core vcc_core vcc_core p i o 1 2 [gpdack0 ] pio11 [gpdack1 ] vcc_i/o vcc_i/o nc trig/ trace ac ad nc nc pio31 [rin2 ] pio26 [gpmem- cs16 ] pio24 [g p d b u - foe ] pio19 [gpirq4] pio18 [gpirq5] pio13 [gpirq10] pio10 [gpdack2 ] pio5 [gpdrq3] pio4 [gptc] nc nc ad ae nc sin1 pio30 [dcd2 ] pio27 [gpcs0 ] pio23 [gpirq0] pio20 [gpirq3] pio17 [gpirq6] pio14 [gpirq9] pio9 [gpdack3 ] pio6 [gpdrq2] pio3 [gpaen] pio0 [gpale] nc ae af nc sout1 pio29 [dsr2 ] pio28 [cts2 ] pio22 [gpirq1] pio21 [gpirq2] pio16 [gpirq7] pio15 [gpirq8] pio8 [gpdrq0] pio7 [gpdrq1] pio2 [gprdy] pio1 [gpbhe ] nc af 12345678910111213
lan?sc520 microcontroller data sheet 9 preliminary connection diagram (continued) 388-pin plastic bga package top view 14 15 16 17 18 19 20 21 22 23 24 25 26 a md7 md23 md9 md25 md11 md27 md28 md13 md14 md30 md31 gnd_anlg vcc_rtc a b md22 md8 md24 md10 md26 clk- memout md12 md29 gpa18 {rstld3} md15 romcs1 [gpcs1 ] bbatsen vcc_anlg b c gpa20 {rstld5} gpd13 gpiowr gpd14 gpmemwr gpa21 {rstld6} pwrgood gpa19 {rstld4} nc romcs2 [gpcs2 ] gpa15 {rstld0} mecc0 mecc4 c d g p d 1 2 v c c _ i / o v c c _ i / o g p d 1 5 vcc_core vcc_core prgreset v c c _ i / o v c c _ i / o n c g pa 1 6 {rstld1} mecc5 mecc1 d e nc gpa17 {rstld2} sweb swea e f gpa7 gpmemrd scasa scasb f g vcc_core g p i o r d sdqm0 sdqm2 g h vcc_core g pa 5 s d q m 3 s d q m 1 h j gpa3 gpa0 scs2 scs3 j k vcc_i/o gpa2 srasa srasb k l gnd gnd gnd vcc_i/o gpa4 ma0 ma1 l m gnd gnd gnd gpa10 gpa8 ma3 ma2 m n gnd gnd gnd gpa11 gpa12 ma4 ma5 n p gnd gnd gnd vcc_core g pa 1 3 m a 7 m a 6 p r gnd gnd gnd vcc_core g pa 1 4 m a 8 m a 9 r t gnd gnd gnd nc nc ba0 ma10 t u sout2 cmdack ba1 ma11 u v vcc_i/o sin2 scs0 ma12 v w vcc_i/o cf_dram [wbmstr2] {cfg2} scs1 mecc2 w y vcc_i/o pitout2 {cfg3} mecc3 mecc6 y aa vcc_i/o tmrin1 [gpcs4 ] rombufoe nc aa ab romrd flashwr bootcs 33mxtal1 ab ac vcc_core vcc_core n c n c v c c _ i / o v c c _ i / o t m r i n 0 [gpcs5 ] pitgate2 [gpcs3 ] gpreset tmrout1 [gpcs6 ] datastrb [wbmstr1] {cfg1} nc 33mxtal2 ac ad nc nc nc nc nc ssi_clk cf_rom_ gpcs [wbmstr0] {cfg0} jtag_tck rts2 tmrout0 [gpcs7 ] br/tc nc nc ad ae nc nc nc nc nc ssi_di nc jtag_tms jtag_trst dtr2 nc nc 32kxtal2 ae af nc nc nc stop/tx nc ssi_do nc jtag_tdi jtag_tdo nc lf_pll1 nc 32kxtal1 af 14 15 16 17 18 19 20 21 22 23 24 25 26
10 lan?sc520 microcontroller data sheet preliminary pin designations this section identifies the pins of the lansc520 micro- controller and lists the signals associated with each pin. in all tables the brackets, [ ], indicate alternate, multi- plexed functions, and braces, { }, indicate reset config- uration pins (pinstraps). the line over a pin name indicates an active low signal. the word pin refers to the physical wire; the word signal refers to the electrical signal that flows through it. n pin designations are listed in the pin designations (pin number) table on page 11 and the pin designations (pin name) table on page 13. n table 2, signal descriptions on page 17 contains a description of the microcontroller signals organized alphabetically by functional group. table 1 on page 16 defines terms used in table 2. the table includes columns listing the multiplexed functions and i/o type. refer to appendix a, pin tables, on page a-1 for an additional group of tables with the following informa- tion: n multiplexed signal tradeoffstable 16 on page a-2. n programmable i/o pins ordered by 1) pio pin number and 2) multiplexed signal name, respectively, including pin numbers, multiplexed functions, and pin configuration following system resettable 17 on page a-4 and table 18 on page a-5. n comprehensive pin and signal summary showing signal name and alternate function, pin number, i/o type, maximum load values, power-on reset default function, reset state, power-on reset default opera- tion, hold state, and voltagetable 20 on page a-7.
lan?sc520 microcontroller data sheet 11 preliminary pin designations (pin number 1 ) pin # signal name pin # signal name pin # signal name pin # signal name pin # signal name a1 ad30 b19 clkmemout d11 vcc_core h23 vcc_core m23 gpa10 a2 ad31 b20 md12 d12 vcc_core h24 gpa5 m24 gpa8 a3 nc b21 md29 d13 gpd11 h25 sdqm3 m25 ma3 a4 clkmemin b22 gpa18{rstld3} d14 gpd12 h26 sdqm1 m26 ma2 a5 rst b23 md15 d15 vcc_i/o j1 ad18 n1 stop a6 clkpciout b24 romcs1 [gpcs1 ] d16 vcc_i/o j2 ad17 n2 perr a7 clktimer [clktest] b25 bbatsen d17 gpd15 j3 intb n3 req1 a8 md1 b26 vcc_anlg d18 vcc_core j4 vcc_i/o n4 gnt1 a9 md17 c1 gpa6 d19 vcc_core j23 gpa3 n11 gnd a10 md3 c2 gpa9 d20 prgreset j24 gpa0 n12 gnd a11 md19 c3 gpa25 {debug_enter} d21 vcc_i/o j25 scs2 n13 gnd a12 md5 c4 gpd0 d22 vcc_i/o j26 scs3 n14 gnd a13 md21 c5 nc d23 nc k1 cbe2 n15 gnd a14 md7 c6 nc d24 gpa16{rstld1} k2 ad16 n16 gnd a15 md23 c7 gpd2 d25 mecc5 k3 inta n23 gpa11 a16 md9 c8 gpd3 d26 mecc1 k4 vcc_i/o n24 gpa12 a17 md25 c9 gpd4 e1 ad25 k23 vcc_i/o n25 ma4 a18 md11 c10 gpd7 e2 ad24 k24 gpa2 n26 ma5 a19 md27 c11 gpd8 e3 nc k25 srasa p1 par a20 md28 c12 gpd9 e4 vcc_core k26 srasb p2 serr a21 md13 c13 gpd10 e23 nc l1 frame p3 gnt2 a22 md14 c14 gpa20{rstld5} e24 gpa17{rstld2} l2 irdy p4 req2 a23 md30 c15 gpd13 e25 sweb l3 req0 p11 gnd a24 md31 c16 gpiowr e26 swea l4 vcc_i/o p12 gnd a25 gnd_anlg c17 gpd14 f1 ad23 l11 gnd p13 gnd a26 vcc_rtc c18 gpmemwr f2 cbe3 l12 gnd p14 gnd b1 ad29 c19 gpa21{rstld6} f3 gpa22{rstld7} l13 gnd p15 gnd b2 ad28 c20 pwrgood f4 vcc_core l14 gnd p16 gnd b3 nc c21 gpa19{rstld4} f23 gpa7 l15 gnd p23 vcc_core b4 nc c22 nc f24 gpmemrd l16 gnd p24 gpa13 b5 gpd1 c23 romcs2 [gpcs2 ] f25 scasa l23 vcc_i/o p25 ma7 b6 nc c24 gpa15{rstld0} f26 scasb l24 gpa4 p26 ma6 b7 md0 c25 mecc0 g1 ad22 l25 ma0 r1 cbe1 b8 md16 c26 mecc4 g2 ad21 l26 ma1 r2 ad15 b9 md2 d1 ad26 g3 clkpciin m1 devsel r3 req3 b10 md18 d2 ad27 g4 gpa1 m2 trdy r4 vcc_core b11 md4 d3 gpa23 {amdebug_dis} g23 vcc_core m3 gnt0 r11 gnd b12 md20 d4 gpa24 {inst_trce} g24 gpiord m4 vcc_i/o r12 gnd b13 md6 d5 vcc_i/o g25 sdqm0 m11 gnd r13 gnd b14 md22 d6 vcc_i/o g26 sdqm2 m12 gnd r14 gnd b15 md8 d7 vcc_i/o h1 ad19 m13 gnd r15 gnd b16 md24 d8 vcc_i/o h2 ad20 m14 gnd r16 gnd b17 md10 d9 gpd5 h3 intc m15 gnd r23 vcc_core b18 md26 d10 gpd6 h4 intd m16 gnd r24 gpa14
12 lan?sc520 microcontroller data sheet preliminary r25 ma8 w3 dtr1 ac5 vcc_core ad13 nc ae21 jtag_tms r26 ma9 w4 rts1 ac6 vcc_core ad14 nc ae22 jtag_trst t1 ad13 w23 vcc_i/o ac7 vcc_core ad15 nc ae23 dtr2 t2 ad14 w24 cf_dram [wbmstr2]{cfg2} ac8 pio12 [gpdack0 ] ad16 nc ae24 nc t3 gnt3 w25 scs1 ac9 pio11[gpdack1 ] ad17 nc ae25 nc t4 vcc_core w26 mecc2 ac10 vcc_i/o ad18 nc ae26 32kxtal2 t11 gnd y1 ad6 ac11 vcc_i/o ad19 ssi_clk af1 nc t12 gnd y2 ad7 ac12 nc ad20 cf_rom_gpcs [wbmstr0]{cfg0} af2 sout1 t13 gnd y3 dsr1 ac13 trig/trace ad21 jtag_tck af3 pio29[dsr2 ] t14 gnd y4 vcc_i/o ac14 vcc_core ad22 rts2 af4 pio28[cts2 ] t15 gnd y23 vcc_i/o ac15 vcc_core ad23 tmrout0 [gpcs7 ] af5 pio22[gpirq1] t16 gnd y24 pitout2{cfg3} ac16 nc ad24 br/tc af6 pio21[gpirq2] t23 nc y25 mecc3 ac17 nc ad25 nc af7 pio16[gpirq7] t24 nc y26 mecc6 ac18 vcc_i/o ad26 nc af8 pio15[gpirq8] t25 ba0 aa1 ad5 ac19 vcc_i/o ae1 nc af9 pio8[gpdrq0] t26 ma10 aa2 ad4 ac20 tmrin0[gpcs5 ] ae2 sin1 af10 pio7[gpdrq1] u1 ad12 aa3 rin1 ac21 pitgate2[gpcs3 ] ae3 pio30[dcd2 ] af11 pio2[gprdy] u2 ad11 aa4 vcc_i/o ac22 gpreset ae4 pio27[gpcs0 ] af12 pio1[gpbhe ] u3 req4 aa23 vcc_i/o ac23 tmrout1[gpcs6 ] ae5 pio23[gpirq0] af13 nc u4 gnt4 aa24 tmrin1[gpcs4 ] ac24 datastrb [wbmstr1]{cfg1} ae6 pio20[gpirq3] af14 nc u23 sout2 aa25 rombufoe ac25 nc ae7 pio17[gpirq6] af15 nc u24 cmdack aa26 nc ac26 33mxtal2 ae8 pio14[gpirq9] af16 nc u25 ba1 ab1 ad2 ad1 nc ae9 pio9[gpdack3 ] af17 stop/tx u26 ma11 ab2 ad3 ad2 nc ae10 pio6[gpdrq2] af18 nc v1 ad9 ab3 nc ad3 pio31[rin2 ] ae11 pio3[gpaen] af19 ssi_do v2 ad10 ab4 nc ad4 pio26 [gpmemcs16 ] ae12 pio0[gpale] af20 nc v3 cts1 ab23 romrd ad5 pio24[gpdbufoe ] ae13 nc af21 jtag_tdi v4 dcd1 ab24 flashwr ad6 pio19[gpirq4] ae14 nc af22 jtag_tdo v23 vcc_i/o ab25 bootcs ad7 pio18[gpirq5] ae15 nc af23 nc v24 sin2 ab26 33mxtal1 ad8 pio13[gpirq10] ae16 nc af24 lf_pll1 v25 scs0 ac1 ad1 ad9 pio10[gpdack2 ] ae17 nc af25 nc v26 ma12 ac2 ad0 ad10 pio5[gpdrq3] ae18 nc af26 32kxtal1 w1 ad8 ac3 nc ad11 pio4[gptc] ae19 ssi_di w2 cbe0 ac4 pio25 [gpiocs16 ] ad12 nc ae20 nc notes: 1. see table 17 on page a-4 for pios sorted by pin number. pin designations (pin number 1 ) (continued) pin # signal name pin # signal name pin # signal name pin # signal name pin # signal name
lan?sc520 microcontroller data sheet 13 preliminary pin designations (pin name 1 ) signal name pin # signal name pin # signal name pin # signal name pin # signal name pin # 32kxtal1 af26 {amdebug_dis} gpa23 d3 gnd l11 gnd_anlg a25 [gpcs1 ]romcs1 b24 32kxtal2 ae26 ba0 t25 gnd l12 gnt0 m3 [gpcs2 ]romcs2 c23 33mxtal1 ab26 ba1 u25 gnd l13 gnt1 n4 [gpcs3 ]pitgate2 ac21 33mxtal2 ac26 bbatsen b25 gnd l14 gnt2 p3 [gpcs4 ]tmrin1 aa24 ad0 ac2 bootcs ab25 gnd l15 gnt3 t3 [gpcs5 ]tmrin0 ac20 ad1 ac1 br/tc ad24 gnd l16 gnt4 u4 [gpcs6 ]tmrout1 ac23 ad2 ab1 cbe0 w2 gnd m11 gpa0 j24 [gpcs7 ]tmrout0 ad23 ad3 ab2 cbe1 r1 gnd m12 gpa1 g4 gpd0 c4 ad4 aa2 cbe2 k1 gnd m13 gpa2 k24 gpd1 b5 ad5 aa1 cbe3 f2 gnd m14 gpa3 j23 gpd2 c7 ad6 y1 cf_dram [wbmstr2]{cfg2} w24 gnd m15 gpa4 l24 gpd3 c8 ad7 y2 cf_rom_gpcs [wbmstr0]{cfg0} ad20 gnd m16 gpa5 h24 gpd4 c9 ad8 w1 {cfg0} cf_rom_gpcs [wbmstr0] ad20 gnd n11 gpa6 c1 gpd5 d9 ad9 v1 {cfg1}datastrb [wbmstr1] ac24 gnd n12 gpa7 f23 gpd6 d10 ad10 v2 {cfg2]cf_dram [wbmstr2} w24 gnd n13 gpa8 m24 gpd7 c10 ad11 u2 {cfg3}pitout2 y24 gnd n14 gpa9 c2 gpd8 c11 ad12 u1 clkmemin a4 gnd n15 gpa10 m23 gpd9 c12 ad13 t1 clkmemout b19 gnd n16 gpa11 n23 gpd10 c13 ad14 t2 clkpciin g3 gnd p11 gpa12 n24 gpd11 d13 ad15 r2 clkpciout a6 gnd p12 gpa13 p24 gpd12 d14 ad16 k2 clktest [clktimer] a7 gnd p13 gpa14 r24 gpd13 c15 ad17 j2 [clktimer] clktest a7 gnd p14 gpa15{rstld0} c24 gpd14 c17 ad18 j1 cmdack u24 gnd p15 gpa16{rstld1} d24 gpd15 d17 ad19 h1 cts1 v3 gnd p16 gpa17{rstld2} e24 [gpdack0 ]pio12 ac8 ad20 h2 [cts2 ]pio28 af4 gnd r11 gpa18{rstld3} b22 [gpdack1 ]pio11 ac9 ad21 g2 datastrb [wbmstr1]{cfg1} ac24 gnd r12 gpa19{rstld4] c21 [gpdack2 ]pio10 ad9 ad22 g1 dcd1 v4 gnd r13 gpa20{rstld5} c14 [gpdack3 ]pio9 ae9 ad23 f1 [dcd2 ]pio30 ae3 gnd r14 gpa21[rstld6} c19 [gpdbufoe ] pio24 ad5 ad24 e2 {debug_enter} gpa25 c3 gnd r15 gpa22{rstld7} f3 [gpdrq0]pio8 af9 ad25 e1 devsel m1 gnd r16 gpa23 {amdebug_dis} d3 [gpdrq1]pio7 af10 ad26 d1 dsr1 y3 gnd t11 gpa24 {inst_trce] d4 [gpdrq2]pio6 ae10 ad27 d2 [dsr2 ]pio29 af3 gnd t12 gpa25 {debug_enter] c3 [gpdrq3]pio5 ad10 ad28 b2 dtr1 w3 gnd t13 [gpaen]pio3 ae11 [gpiocs16 ]pio25 ac4 ad29 b1 dtr2 ae23 gnd t14 [gpale]pio0 ae12 gpiord g24 ad30 a1 flashwr ab24 gnd t15 [gpbhe ]pio1 af12 gpiowr c16 ad31 a2 frame l1 gnd t16 [gpcs0 ]pio27 ae4 [gpirq0]pio23 ae5
14 lan?sc520 microcontroller data sheet preliminary [gpirq1]pio22 af5 ma8 r25 md31 a24 nc ae24 pio12[gpdack0 ] ac8 [gpirq2]pio21 af6 ma9 r26 mecc0 c25 nc ae25 pio13[gpirq10] ad8 [gpirq3]pio20 ae6 ma10 t26 mecc1 d26 nc af1 pio14[gpirq9] ae8 [gpirq4]pio19 ad6 ma11 u26 mecc2 w26 nc af13 pio15[gpirq8] af8 [gpirq5]pio18 ad7 ma12 v26 mecc3 y25 nc af14 pio16[gpirq7] af7 [gpirq6]pio17 ae7 md0 b7 mecc4 c26 nc af15 pio17[gpirq6] ae7 [gpirq7]pio16 af7 md1 a8 mecc5 d25 nc af16 pio18[gpirq5] ad7 [gpirq8]pio15 af8 md2 b9 mecc6 y26 nc af18 pio19[gpirq4] ad6 [gpirq9]pio14 ae8 md3 a10 nc a3 nc af20 pio20[gpirq3] ae6 [gpirq10]pio13 ad8 md4 b11 nc aa26 nc af23 pio21[gpirq2] af6 [gpmemcs16 ] pio26 ad4 md5 a12 nc ab3 nc af25 pio22[gpirq1] af5 gpmemrd f24 md6 b13 nc ab4 nc b3 pio23[gpirq0] ae5 gpmemwr c18 md7 a14 nc ac3 nc b4 pio24 [gpdbufoe ] ad5 [gprdy]pio2 af11 md8 b15 nc ac12 nc b6 pio25 [gpiocs16 ] ac4 gpreset ac22 md9 a16 nc ac16 nc c5 pio26 [gpmemcs16 ] ad4 [gptc]pio4 ad11 md10 b17 nc ac17 nc c6 pio27[gpcs0 ] ae4 {inst_trce} gpa24 d4 md11 a18 nc ac25 nc c22 pio28[cts2 ] af4 inta k3 md12 b20 nc ad1 nc d23 pio29[dsr2 ] af3 intb j3 md13 a21 nc ad2 nc e3 pio30[dcd2 ] ae3 intc h3 md14 a22 nc ad12 nc e23 pio31[rin2 ] ad3 intd h4 md15 b23 nc ad13 nc t23 pitgate2 [gpcs3 ] ac21 irdy l2 md16 b8 nc ad14 nc t24 pitout2{cfg3} y24 jtag_tck ad21 md17 a9 nc ad15 par p1 prgreset d20 jtag_tdi af21 md18 b10 nc ad16 perr n2 pwrgood c20 jtag_tdo af22 md19 a11 nc ad17 pio0[gpale] ae12 req0 l3 jtag_tms ae21 md20 b12 nc ad18 pio1[gpbhe ] af12 req1 n3 jtag_trst ae22 md21 a13 nc ad25 pio2[gprdy] af11 req2 p4 lf_pll1 af24 md22 b14 nc ad26 pio3[gpaen] ae11 req3 r3 ma0 l25 md23 a15 nc ae1 pio4[gptc] ad11 req4 u3 ma1 l26 md24 b16 nc ae13 pio5[gpdrq3] ad10 rin1 aa3 ma2 m26 md25 a17 nc ae14 pio6[gpdrq2] ae10 [rin2 ]pio31 ad3 ma3 m25 md26 b18 nc ae15 pio7[gpdrq1] af10 rombufoe aa25 ma4 n25 md27 a19 nc ae16 pio8[gpdrq0] af9 romcs1 [gpcs1 ]b24 ma5 n26 md28 a20 nc ae17 pio9[gpdack3 ]ae9 romcs2 [gpcs2 ] c23 ma6 p26 md29 b21 nc ae18 pio10[gpdack2 ] ad9 romrd ab23 ma7 p25 md30 a23 nc ae20 pio11[gpdack1 ] ac9 rst a5 pin designations (pin name 1 ) (continued) signal name pin # signal name pin # signal name pin # signal name pin # signal name pin #
lan?sc520 microcontroller data sheet 15 preliminary {rstld0}gpa15 c24 sdqm1 h26 tmrin0[gpcs5 ] ac20 vcc_core f4 vcc_i/o d15 {rstld1}gpa16 d24 sdqm2 g26 tmrin1[gpcs4 ] aa24 vcc_core g23 vcc_i/o d16 {rstld2}gpa17 e24 sdqm3 h25 tmrout0 [gpcs7 ] ad23 vcc_core h23 vcc_i/o d21 {rstld3}gpa18 b22 serr p2 tmrout1 [gpcs6 ] ac23 vcc_core p23 vcc_i/o d22 {rstld4}gpa19 c21 sin1 ae2 trdy m2 vcc_core r23 vcc_i/o j4 {rstld5}gpa20 c14 sin2 v24 trig/trace ac13 vcc_core r4 vcc_i/o k23 {rstld6}gpa21 c19 sout1 af2 vcc_anlg b26 vcc_core t4 vcc_i/o k4 {rstld7}gpa22 f3 sout2 u23 vcc_core ac5 vcc_i/o aa23 vcc_i/o l4 rts1 w4 srasa k25 vcc_core ac6 vcc_i/o aa4 vcc_i/o l23 rts2 ad22 srasb k26 vcc_core ac7 vcc_i/o ac10 vcc_i/o m4 scasa f25 ssi_clk ad19 vcc_core ac14 vcc_i/o ac11 vcc_i/o v23 scasb f26 ssi_di ae19 vcc_core ac15 vcc_i/o ac18 vcc_i/o w23 scs0 v25 ssi_do af19 vcc_core d11 vcc_i/o ac19 vcc_i/o y4 scs1 w25 stop n1 vcc_core d12 vcc_i/o d5 vcc_i/o y23 scs2 j25 stop/tx af17 vcc_core d18 vcc_i/o d6 vcc_rtc a26 scs3 j26 swea e26 vcc_core d19 vcc_i/o d7 [wbmstr0]{cfg0} cf_rom_gpcs ad20 sdqm0 g25 sweb e25 vcc_core e4 vcc_i/o d8 [wbmstr1]{cfg1} datastrb ac24 [wbmstr2]{cfg2} cf_dram w24 notes: 1. see table 17 on page a-4 for pios sorted by pin number. pin designations (pin name 1 ) (continued) signal name pin # signal name pin # signal name pin # signal name pin # signal name pin #
16 lan?sc520 microcontroller data sheet preliminary signal descriptions table 2, signal descriptions on page 17 contains a description of the lansc520 microcontroller signals. the microcontroller contains 258 signal pins in addition to power and ground pins in a plastic ball grid array (pbga) package. table 1 describes the terms used in the signal descrip- tion table. the signals are organized alphabetically within the following functional groups: n synchronous dram (page 17) n rom/flash (page 18) n pci bus (page 18) n gp bus (page 19) n serial ports (page 21) n clocks and reset (page 22) n jtag (page 23) n amdebug? interface (page 23) n system test (page 23) n chip selects (page 24) n programmable i/o (pio) (page 25) n timers (page 25) n configuration (page 26) n power (page 27) table 1. signal descriptions table definitions term definition general terms [ ] indicates the pin alternate function; a pin defaults to the signal named without the brackets. { } indicates the reset configuration pin (pinstrap). pin refers to the physical wire. signal refers to the electrical signal that flows across a pin. signal a line over a signal name indicates that the signal is active low; a signal name without a line is active high. signal types analog analog voltage b bidirectional hhigh i input ls programmable to hold last state of pin o totem pole output o/ts totem pole output/three-state output od open-drain output od-o open-drain output or totem pole output osc oscillator pd internal pulldown resistor (~100C150 k w) power power pins pu internal pullup resistor (~100C150 k w) sti schmitt trigger input sti-od schmitt trigger input or open-drain output ts three-state output
lan?sc520 microcontroller data sheet 17 preliminary table 2. signal descriptions signal multiplexed signal type description synchronous dram ba1Cba0 o bank address is the sdram bank address bus. clkmemin i sdram clock input is the sdram clock return signal used to minimize skew between the internal sdram clock and the clkmemout signal provided to the sdram devices. this signal compensates for buffer and load delays introduced by the board design. clkmemout o sdram clock output is the 66-mhz clock that provides clock signaling for the synchronous dram devices. this clock may require an external low skew buffer for system implementations that result in heavy loading on the sdram clock signal. ma12Cma0 o sdram address is the sdram multiplexed address bus. md31Cmd0 b sdram data bus inputs data during sdram read cycles and outputs data during sdram write cycles. mecc6Cmecc0 b memory error correction code contains the ecc checksum (syndrome) bits used to validate and correct data errors. scasa Cscasb o column address strobes are used in combination with the srasa C srasb and swea Csweb to encode the sdram command type. scasa and scasb are the same signal provided on two different pins to reduce the total load connected to cas . suggested system connection: scasa for sdram banks 0 and 1 scasb for sdram banks 2 and 3 scs3 Cscs0 o sdram chip selects are the sdram chip-select outputs. these signals are asserted to select a bank of sdram devices. the chip- select signals enable the sdram devices to decode the commands asserted via srasa Csrasb , scasa Cscasb , and swea Csweb . sdqm3Csdqm0 o data input/output masks make sdram data output high-impedance and blocks data input on sdram while active. each of the four sdqm3Csdqm0 signals is associated with one byte of four throughout the array. each sdqmx signal provides an input mask signal for write accesses and an output enable signal for read accesses. srasa Csrasb o row address strobes are used in combination with the scasa C scasb and swea Csweb to encode the sdram command type. srasa and srasb are the same signal provided on two different pins to reduce the total load connected to ras . suggested system connection: srasa for sdram banks 0 and 1 srasb for sdram banks 2 and 3 swea Csweb o sdram memory write enables are used in combination with the srasa Csrasb and scasa Cscasb to encode the sdram command type. swea and sweb are the same signal provided on two different pins to reduce the total load connected to we. suggested system connection: swea for sdram banks 0 and 1 sweb for sdram banks 2 and 3
18 lan?sc520 microcontroller data sheet preliminary rom/flash bootcs o rom/flash boot chip select is an active low output that provides the chip select for the startup rom and/or the rom/flash array (bios, hal, o/s, etc.). the bootcs signal asserts for accesses made to the 64-kbyte segment that contains the am5 x 86 cpu boot vector: addresses 3ff0000hC3ffffffh. in addition to this linear decode region, bootcs asserts in response to accesses to user- programmable address regions. flashwr o flash write indicates that the current cycle is a write of the selected flash device. when this signal is asserted, the selected flash device can latch data from the data bus. gpa25Cgpa0 o general-purpose address bus provides the address to the systems rom/flash devices. it is also the address bus for the gp bus devices. twenty-six address lines provide a maximum addressable space of 64 mbytes for each rom chip select. gpd15Cgpd0 b general-purpose data bus inputs data during memory and i/o read cycles and outputs data during memory and i/o write cycles. a reset configuration pin (cfg2) allows the gp bus to be used for the boot chip-select rom interface. configuration registers are used to select whether romcs2 and romcs1 use the gp bus data bus or the md data bus. the gp data bus supports 16-bit or 8-bit rom interfaces. two data buses are selectable to facilitate the use of rom in a mixed voltage system. md31Cmd0 b memory data bus inputs data during sdram read cycles and outputs data during sdram write cycles. configuration registers are used to select whether romcs2 and romcs1 use the gp bus data bus or the md data bus. a reset configuration pin (cfg2) allows the gp data bus to be used for boot cs . the memory data bus supports an 8-, 16-, or 32-bit rom interface. rombufoe o rom buffer output enable is an optional signal used to enable a buffer to the rom/flash devices if they need to be isolated from the lansc520 microcontroller, other gp bus devices, or sdram system for voltage or loading considerations. this signal asserts for all accesses through the rom controller. the buffer direction is controlled by the romrd or f lashw r signal. romcs2 [gpcs2 ]o rom/flash chip selects are signals that can be programmed to be asserted for accesses to user-programmable address regions. romcs1 [gpcs1 ]o romrd o rom/flash read indicates that the current cycle is a read of the selected rom/flash device. when this signal is asserted, the selected rom device can drive data onto the data bus. peripheral component interconnect (pci) bus ad31Cad0 b pci address data bus is the pci time-multiplexed address/data bus. cbe3 Ccbe0 b command or byte-enable bus functions 1) as a time-multiplexed bus command that defines the type of transaction on the ad bus, or 2) as byte enables: cbe0 for ad7Cad0 cbe1 for ad15Cad8 cbe2 for ad23Cad16 cbe3 for ad31Cad24 clkpciin i pci bus clock input is the 33-mhz pci bus clock. this pin can be connected to the clkpciout pin for systems where the lansc520 microcontroller is the source of the pci bus clock. table 2. signal descriptions (continued) signal multiplexed signal type description
lan?sc520 microcontroller data sheet 19 preliminary clkpciout o pci bus clock output is a 33-mhz clock output for the pci bus devices. this signal is derived from the 33mxtal1/33mxtal2 interface. devsel b device select is asserted by the target when it has decoded its address as the target of the current transaction. frame b frame is driven by the transaction initiator to indicate the start and duration of the transaction. gnt4 Cgnt0 o bus grants are asserted by the lansc520 microcontroller to grant access to the bus. inta Cintd i interrupt requests are asserted to request an interrupt. these four interrupts are the same type of interrupt as the gpirq10Cgpirq0 signals, and they go to the same interrupt controller. they are named int x to match the common pci interrupt naming convention. configuration registers allow inversion of these interrupt requests to recognize active low interrupt requests. these interrupt requests can be routed to generate nmi. irdy b initiator ready is asserted by the current bus master to indicate that data is ready on the bus (write) or that the master is ready to accept data (read). pa r b pci parity is driven by the initiator or target to indicate parity on the ad31Cad0 and cbe3 Ccbe0 buses. perr b parity error is asserted to indicate a pci bus data parity error in the previous clock cycle. req4 Creq0 i bus requests are asserted by the master to request access to the bus. rst o reset is asserted to reset the pci devices. serr i system error is used for reporting address parity errors or any other system error where the result is catastrophic. stop b stop is asserted by the target to request that the current bus transaction be stopped. trdy b target ready is asserted by the currently addressed target to indicate its ability to complete the current data phase of a transaction. general-purpose bus (gp bus) gpa14Cgpa0 o general-purpose address bus outputs the physical memory or i/o port address. twenty-six address lines provide a maximum addressable space of 64 mbytes. this bus also provides the address to the systems rom/flash devices. gpa15 {rstld0} o{i} gpa16 {rstld1} o{i} gpa17 {rstld2} o{i} gpa18 {rstld3} o{i} gpa19 {rstld4} o{i} gpa20 {rstld5} o{i} gpa21 {rstld6} o{i} gpa22 {rstld7} o{i} gpa23 {amdebug_dis} o{i} gpa24 {inst_trce} o{i} gpa25 {debug_enter} o{i} table 2. signal descriptions (continued) signal multiplexed signal type description
20 lan?sc520 microcontroller data sheet preliminary [gpaen] pio3 o gp bus address enable indicates that the current address on the gpa25Cgpa0 address bus is a memory address, and that the current cycle is a dma cycle. all i/o devices should use this signal in decoding their i/o addresses and should not respond when this signal is asserted. when gpaen is asserted, the gpdackx signals are used to select the appropriate i/o device for the dma transfer. gpaen also asserts when a dma cycle is occurring internally. [gpale] pio0 o gp bus address latch enable is driven at the beginning of a gp bus cycle with valid address. this signal can be used by external devices to latch the gp address for the current cycle. [gpbhe ]pio1 o gp bus byte high enable is driven active when data is to be transferred on the upper 8 bits of the gp data bus. gpd15Cgpd0 b general-purpose data bus inputs data during memory and i/o read cycles, and outputs data during memory and i/o write cycles. [gpdack0 ]pio12 o gp bus dma acknowledge can each be mapped to one of the seven available dma channels. they are asserted active low to acknowledge the corresponding dma requests. [gpdack1 ]pio11 o [gpdack2 ]pio10 o [gpdack3 ]pio9 o [gpdbufoe ]pio24 o gp bus data bus buffer output enable is used to control the output enable on an external transceiver that may be on the gp data bus. using this transceiver is optional in the system design and is necessary only to alleviate loading or voltage issues. this pin is asserted for all external gp bus accesses. it is not asserted during accesses to the internal peripherals even if gp bus echo mode is enabled. note that if the rom is configured to use the gp data bus, then its bytes are not controlled by this buffer enable; they are controlled by the rombufoe signal. [gpdrq0] pio8 i gp bus dma request can each be mapped to one of the seven available dma channels. they are asserted active high to request dma service. [gpdrq1] pio7 i [gpdrq2] pio6 i [gpdrq3] pio5 i [gpiocs16 ] pio25 sti gp bus i/o chip-select 16 is driven active early in the cycle by the targeted i/o device on the gp bus to request a 16-bit i/o transfer. gpiord o gp bus i/o read indicates that the current cycle is a read of the currently addressed i/o device on the gp bus. when this signal is asserted, the selected i/o device can drive data onto the data bus. gpiowr o gp bus i/o write indicates that the current cycle is a write of the currently addressed i/o device on the gp bus. when this signal is asserted, the selected i/o device can latch data from the data bus. table 2. signal descriptions (continued) signal multiplexed signal type description
lan?sc520 microcontroller data sheet 21 preliminary [gpirq0] pio23 i gp bus interrupt request can each be mapped to one of the available interrupt channels or nmi. they are asserted when a peripheral requires interrupt service. configuration registers allow inversion of these interrupt requests to recognize active low interrupt requests. these interrupt requests can be routed to generate nmi. [gpirq1] pio22 i [gpirq2] pio21 i [gpirq3] pio20 i [gpirq4] pio19 i [gpirq5] pio18 i [gpirq6] pio17 i [gpirq7] pio16 i [gpirq8] pio15 i [gpirq9] pio14 i [gpirq10] pio13 i [gpmemcs16 ] pio26 sti gp bus memory chip-select 16 is driven active early in the cycle by the targeted memory device on the gp bus to request a 16-bit memory transfer. [gpmemrd ] o gp bus memory read indicates that the current gp bus cycle is a read of the selected memory device. when this signal is asserted, the selected memory device can drive data onto the data bus. [gpmemwr ]o gp bus memory write indicates that the current gp bus cycle is a write of the selected memory device. when this signal is asserted, the selected memory device can latch data from the data bus. [gprdy] pio2 sti gp bus ready can be driven by open-drain devices. when pulled low during a gp bus access, wait states are inserted in the current cycle. this pin has an internal weak pullup that should be supplemented by a stronger external pullup for faster rise time. gpreset o gp bus reset , when asserted, re-initializes to reset state all devices connected to the gp bus. [gptc] pio4 o gp bus terminal count is driven from the internal dma controller to indicate that the transfer count for the currently active dma channel has reached zero, and that the current dma cycle is the last transfer. serial ports cts1 i clear to send is driven back to the serial port to indicate that the external data carrier equipment (dce) is ready to accept data. [cts2 ]pio28 i dcd1 i data carrier detect is driven back to the serial port from a piece of dce when it has detected a carrier signal from a communications target. [dcd2 ]pio30 i dsr1 i data set ready is used to indicate that the external dce is ready to establish a communication link with the internal serial port controller. [dsr2 ]pio29 i dtr2 Cdtr1 o data terminal ready indicates to the external dce that the internal serial port controller is ready to communicate. rin1 i ring indicate is used by an external modem to inform the serial port that a ring signal was detected. [rin2 ]pio31 i rts2 Crts1 o request to send indicates to the external dce that the internal serial port controller is ready to send data. sin2Csin1 i serial data in is used to receive the serial data from the external serial device or dce into the internal serial port controller. sout2Csout1 o serial data out is used to transmit the serial data from the internal serial port controller to the external serial device or dce. table 2. signal descriptions (continued) signal multiplexed signal type description
22 lan?sc520 microcontroller data sheet preliminary ssi_clk o ssi clock is driven by the lansc520 microcontroller ssi port during active ssi transmit or receive transactions. the idle state of the clock and the assertion/sample edge are configurable. ssi_di sti ssi data input receives incoming data from a peripheral device ssi port. data is shifted in on the opposite ssi_clk signal edge in which ssi_do drives data. ssi_do and ssi_di can be tied together to interface to a three-pin ssi peripheral. ssi_do od ssi data output drives data to a peripheral device ssi port. data is driven on the opposite ssi_clk signal edge in which ssi_di latches data. the do signal is normally at high-impedance when no transmit transaction is active on the ssi port. clocks and reset 32kxtal2C 32kxtal1 osc 32.768-khz crystal interface is used for connecting an external crystal or oscillator to the lansc520 microcontroller. this clock source is used to clock the real-time clock (rtc). in addition, internal plls generate clocks for the timers and uarts based on this clock source. when an external oscillator is used, 32kxtal1 should be grounded and the clock source driven on 32kxtal2. 33mxtal2C 33mxtal1 osc 33-mhz crystal interface is the main system clock for the chip. this clock source is used to derive the sdram, cpu, and pci clocks. when an external oscillator is used, 33mxtal1 should be unconnected and the clock source driven on 33mxtal2. [clktest] clktimer o test clock output is a shared pin that allows many of the internal clocks to be driven externally. clktest can drive the internal clocks of the uarts, pll1, pll2, the programmable interval timer (pit), or the real-time clock (rtc) for testing or for driving an external device. clktimer [clktest] i timer clock input is a shared clock pin that can be used to input a frequency to the programmable interval timer (pit). lf_pll1 i loop filter interface is used for connecting external loop filter components. component values and circuit descriptions are contained in clock generation and control on page 38. prgreset sti programmable reset can be programmed to reset the lansc520 microcontroller, but allow sdram refresh to continue during the reset. this allows the system to be reset without losing the information stored in sdram. on power-up, prgreset is disabled and must be programmed to be operational. when disabled, this pin has no effect on the lansc520 microcontroller. pwrgood sti power good is a reset signal that indicates to the lansc520 microcontroller that the v cc levels are within the normal operation range. it is used to reset the entire chip and must be held low for one second after all v cc signals (except vcc_rtc) on the chip are high. this signal must be returned low before the v cc signals degrade to put the rtc into the correct state for operation in rtc-only mode. table 2. signal descriptions (continued) signal multiplexed signal type description
lan?sc520 microcontroller data sheet 23 preliminary jtag jtag_tck i test clock is the input clock for test access port. jtag_tdi i test data input is the serial input stream for input data. this pin has a weak internal pullup resistor. it is sampled on the rising edge of jtag_tck. if not driven, this input is sampled high internally. jtag_tdo o/ts test data output is the serial output stream for result data. it is in the high-impedance state except when scanning is in progress. jtag_tms i test mode select is an input for controlling the test access port. this pin has a weak internal pullup resistor. if it is not driven, it is sampled high internally. jtag_trst i jtag reset is the test access port (tap) reset. this pin has a weak internal pulldown resistor. if not driven, this input is sampled low internally and causes the tap controller logic to remain in the reset state. amdebug interface br/tc i break request/trace capture requests entry to amdebug technology mode. the amdebug technology serial/parallel interface can reconfigure this pin to turn instruction trace capture on or off. cmdack o command acknowledge indicates command completion status. it is asserted high when the in-circuit emulator logic is ready to receive new commands from the host. it is driven low when the in-circuit emulator core is executing a command from the host and remains low until the command is completed. stop/tx o stop/transmit is asserted high on entry to amdebug mode. during normal mode, this is set high when there is data to be transmitted to the host (during operating system/application communication). trig/trace o trigger/trace triggers events to a logic analyzer (optional, from am5 x 86 cpu debug registers) or indicates trace on or off status. the amdebug technology is used to enable and configure this pin. system test cf_dram [wbmstr2] {cfg2} o{i} code fetch sdram, during sdram reads, provides code fetch status. when low, this indicates that the current sdram read is a cpu code fetch demanded by the cpu, or a read prefetch initiated due to a demand code fetch by the cpu. when high during reads, this indicates that the sdram read is not a code fetch, and it could have been initiated by the cpu, pci master, or the gp bus gp-dma controller, either demand or prefetch. during sdram write cycles this pin provides an indication of the source of the data, either gp-dma controller/pci bus master or cpu. when high, this indicates that either a gp bus dma initiator or an external pci bus master contributed to the current sdram write cycle (the cpu may also have contributed). a low indicates that the cpu is the only master that contributed to this write cycle. cf_rom_gpcs [wbmstr0] {cfg0} o{i} code fetch rom/gpcs provides an indication that the cpu is performing a code fetch from rom (on either the gp bus or sdram data bus), or from any gp csx pin. when low during a read cycle (as indicated by either gpmemrd or romrd ), the cpu is performing a code fetch from rom or a gp bus chip select. at all other times (including writes), this signal is high. datastrb [wbmstr1] {cfg1} o{i} data strobe is a debug signal that is asserted to allow the external system to latch sdram data. this can be used to trace data on the sdram interface with an in-circuit emulator probe or logic analyzer. table 2. signal descriptions (continued) signal multiplexed signal type description
24 lan?sc520 microcontroller data sheet preliminary [wbmstr0] cf_rom_gpcs {cfg0} o{i} write buffer master indicates which block(s) wrote to a rank in the write buffer (during sdram write cycles) and which block is reading from sdram (during sdram read cycles). wbmstr0 , when a logical 1, indicates that the internal gp bus dma controller has contributed to the write buffer rank (write cycles) or is reading from sdram (read cycles). [wbmstr1] datastrb {cfg1} o{i} wbmstr1 , when a logical 1, indicates that the pci master has contributed to the write buffer rank (write cycles) or is reading from sdram (read cycles). [wbmstr2] cf_dram {cfg2} o{i} wbmstr2 , when a logical 1, it indicates that the cpu has contributed to the write buffer rank (write cycles) or is reading from sdram (read cycles). chip selects [gpcs0 ]pio27 o general-purpose chip select signals are for the gp bus. they can be used for either memory or i/o accesses. these chip selects are asserted for am5 x 86 cpu accesses to the corresponding regions set up in the programmable address region (par) registers. [gpcs1 ]romcs1 o [gpcs2 ]romcs2 o [gpcs3 ]pitgate2 o [gpcs4 ]tmrin1 o [gpcs5 ]tmrin0 o [gpcs6 ]tmrout1 o [gpcs7 ]tmrout0 o table 2. signal descriptions (continued) signal multiplexed signal type description
lan?sc520 microcontroller data sheet 25 preliminary programmable i/o (pio) pio0 [gpale] b programmable input/output signals can be programmed as inputs or outputs. when they are outputs, they can be driven high or low by programming bits in registers. pio1 [gpbhe ]b pio2 [gprdy] b pio3 [gpaen] b pio4 [gptc] b pio5 [gpdrq3] b pio6 [gpdrq2] b pio7 [gpdrq1] b pio8 [gpdrq0] b pio9 [gpdack3 ]b pio10 [gpdack2 ]b pio11 [gpdack1 ]b pio12 [gpdack0 ]b pio13 [gpirq10] b pio14 [gpirq9] b pio15 [gpirq8] b pio16 [gpirq7] b pio17 [gpirq6] b pio18 [gpirq5] b pio19 [gpirq4] b pio20 [gpirq3] b pio21 [gpirq2] b pio22 [gpirq1] b pio23 [gpirq0] b pio24 [gpdbufoe ]b pio25 [gpiocs16 ]b pio26 [gpmemcs16 ]b pio27 [gpcs0 ]b pio28 [cts2 ]b pio29 [dsr2 ]b pio30 [dcd2 ]b pio31 [rin2 ]b timers pitgate2 [gpcs3 ]i programmable interval timer 2 gate provides control for the pit channel 2. programmable interval timer 2 output is output from the pit channel 2. this signal is typically used as the pc speaker signal. pitout2 {cfg3} o{i} tmrin0 [gpcs5 ]i timer inputs 0 and 1 can be programmed to be the control or clock for the general-purpose (gp) timers 0 and 1. tmrin1 [gpcs4 ]i tmrout0 [gpcs7 ]o timer outputs 0 and 1 are outputs from two of the gp timers. these outputs can be used as pulse-width modulation signals. tmrout1 [gpcs6 ]o table 2. signal descriptions (continued) signal multiplexed signal type description
26 lan?sc520 microcontroller data sheet preliminary configuration {amdebug_dis} gpa23 i amdebug disable is an active high configuration signal latched at the assertion of power good (pwrgood). this pin has a built-in pulldown resistor. at power good assertion: low = normal operation, mode can be enabled by software. high = amdebug mode is disabled and cannot be enabled by software. {cfg0} cf_rom_gpcs [wbmstr0] i configuration inputs 3C0 are latched into the chip when pwrgood is asserted. these signals are all shared with other features. these signals have built-in pulldown resistors. cfg0: choose 8-, 16-, or 32-bit rom/flash interface for bootcs . {cfg1} datastrb [wbmstr1] i cfg1: choose 8-, 16-, or 32-bit rom/flash interface for bootcs . {cfg2} cf_dram [wbmstr2] i cfg2 : when low when pwrgood is asserted, the lansc520 microcontroller uses the gp data bus for bootcs. when seen as high during pwrgood assertion, the bootcs access is across the sdram data bus. default is low (by a built-in pulldown resistor). {cfg3} pitout2 i cfg3 (internal amd test mode enable) : for normal lansc520 microcontroller operation, do not pull high during reset. {debug_enter} gpa25 i enter amdebug mode is an active high configuration signal latched at the assertion of power good (pwrgood). this pin enables the amdebug mode, which causes the processor to fetch and execute one instruction from the bootcs device, and then enter amdebug mode where the cpu waits for debug commands to be delivered by the jtag port. this pin has a built-in pulldown resistor. at pwrgood assertion: high = amdebug mode enabled low = normal operation {inst_trce} gpa24 i instruction trace is an active high configuration signal latched at the assertion of power good (pwrgood). enables trace record generation from power good assertion. this pin has a built-in pulldown resistor. at pwrgood assertion: high = trace controller enabled to output trace records low = normal operation table 2. signal descriptions (continued) signal multiplexed signal type description cfg1 cfg0 bootcs data width 00 8-bit 0 1 16-bit 1 x (dont care) 32-bit
lan?sc520 microcontroller data sheet 27 preliminary {rstld0} gpa15 i reset latched inputs are shared signals that are latched into a register when pwrgood is asserted. they are used to input static information to software (i.e., board revision). these signals have built- in pulldown resistors. {rstld1} gpa16 i {rstld2} gpa17 i {rstld3} gpa18 i {rstld4} gpa19 i {rstld5} gpa20 i {rstld6} gpa21 i {rstld7} gpa22 i power bbatsen analog backup battery sense is a pin on which real-time clock (rtc) backup battery voltage is sampled each time pwrgood is asserted. if this pin samples below 2.0 v, the valid ram and time (vrt) bit in rtc index 0dh is cleared until read. after the read, the vrt bit is set until bbatsen is sensed via a subsequent pwrgood assertion. bbatsen also provides a power-on-reset signal for the rtc when an rtc backup battery is applied for the first time. vcc_anlg power analog power supply for the analog circuits (plls). vcc_core power power supply for the lansc520 microcontroller core logic. vcc_i/o power power supply to the i/o pad ring. vcc_rtc power power supply for the real-time clock and 32-khz oscillator. gnd power digital ground for the remaining lansc520 microcontroller core logic. gnd_anlg power analog ground for the analog circuits. table 2. signal descriptions (continued) signal multiplexed signal type description
28 lan?sc520 microcontroller data sheet preliminary architectural overview the lansc520 microcontroller was designed to provide: n a balanced mix of high performance and low-cost interface mechanisms n a high-performance, industry-standard 32-bit pci bus n glueless interfacing to many 8- and 16-bit i/o pe- ripherals and an 8- and 16-bit bus with programma- ble timing n a cost-effective system architecture that meets a wide range of performance criteria while retaining the lower cost of a 32-bit system n a high degree of leverage from present day hard- ware and software technologies figure 1 on page 29 illustrates the integrated am5 x 86 cpu, bus structure, and on-chip peripherals of the lansc520 microcontroller. three primary interfaces are provided: n a high-performance, 66-mhz, 32-bit synchronous dram (sdram) interface of up to 256 mbytes is used for am5 x 86 cpu code execution, as well as buffer storage of external pci bus masters and gp bus dma initiators. a high-performance rom/flash interface can also be connected to the sdram in- terface. n an industry-standard, 32-bit pci bus is provided for high bandwidth i/o peripherals such as local area network controllers, synchronous communications controllers, and disk storage controllers. n a simple 8/16-bit, 33-mhz general-purpose bus (gp bus) provides a glueless connection to lower bandwidth peripherals and nvram, sram, rom, or custom asics; supports dynamic bus sizing and compatibility with many common isa devices. these three buses listed above are provided in all op- erating modes of the lansc520 microcontroller. in addition to these three primary interfaces, the lansc520 microcontroller also contains internal oscil- lator circuitry and phase locked loop (pll) circuitry, re- quiring only two simple crystals for virtually all system clock generation. diagrams showing how the lansc520 microcontroller can be used in various system designs are included in applications on page 33.
lan?sc520 microcontroller data sheet 29 preliminary figure 1. lan?sc520 microcontroller block diagram read/write buffers address cpu bus interface am5 x 86 ? cpu bus interface unit cpu bus interface pci ta r g e t pci master pci bus arbiter cpu bus arbiter clock generation fifos and fifo control gp-dma address data control/status cpu data bus cpu address bus cpu control/status bus gp bus amdebug? technology and jtag request and grant pci bus pci requests and grants gp bus controller rom/flash controller sdram controller cpu request external gp bus gp-dma controller lan?sc520 microcontroller programmable interrupt controller programmable interval timer watchdog timer real-time clock cmos ram general-purpose timers software timer 16550 uart 16550 uart synchronous serial interface programmable i/o controls pc/at compatibility logic decode unit read/write buffers
30 lan?sc520 microcontroller data sheet preliminary industry-standard x86 architecture the am5 x 86 cpu in the lansc520 microcontroller utilizes the industry-standard x86 microprocessor in- struction set that enables compatibility across a variety of performance levels from the 16-bit am186? proces- sors to the high-end amd athlon? processor. soft- ware written for the x86 architecture family is compatible with the lansc520 microcontroller. other benefits of the am5 x 86 cpu include: n improved time-to-market and easy software migra- tion n existing availability of multiple operating systems that directly support the x86 architecture. whether the application requires a real-time operating sys- tem (rtos) or one of the popular microsoft ? oper- ating systems, the lansc520 microcontroller provides consistent compatibility with many off-the- shelf operating systems. n multiple sources of field-proven development tools n integrated floating point unit (fpu) (compliant with ansi/ieee 754 standard) n 16-kbyte unified cache configurable for either write- back or write-through cache mode amdebug? technology for advanced debugging the lansc520 microcontroller provides support for low-cost, full-featured, in-circuit emulation capability. this in-circuit emulation support was developed at amd specifically to enable users to test and debug their software earlier in the design cycle. utilizing this capability, the software can be more extensively exer- cised, and at full execution speeds. it also allows trac- ing during execution from the am5 x 86 cpus internal cache. amdebug technology provides the product design team with two different communication paths on the lansc520 microcontroller, each of which is supported by powerful debug tools from third-party vendors in amds fusione86 sm program. n serial amdebug technology uses a serial connec- tion based on an enhanced jtag protocol and an inexpensive 12-pin connector that can be placed on each board design. this low-cost solution satisfies the requirement of a large number of software de- velopers. n parallel amdebug technology uses a parallel debug port to exchange commands and data between the lansc520 microcontroller and the host. the higher pin count requires that the extra signal pins be provided on a special bond-out package of the lansc520 microcontroller, which is only made available to tool developers such as in-circuit emu- lator manufacturers. the parallel amdebug port greatly simplifies the task of supporting high speed data exchange. industry-standard pci bus interface the lansc520 microcontroller provides a 33-mhz, 32-bit pci bus revision 2.2-compliant host bridge in- terface, including integrated write-posting and read- buffering capabilities suitable for high-throughput appli- cations. the pci host bridge leverages standard pe- ripherals and software. it also provides: n high throughput (132 mbytes/s peak transfer rate) n deep buffering and support for burst transactions from pci bus masters to sdram n flexible arbitration mechanism n support for up to five external pci masters high-performance sdram controller the lansc520 microcontroller provides an integrated sdram controller that supports popular industry-stan- dard synchronous drams (sdram). n the sdram controller interfaces with sdram chips as well as with most standard dimms to en- able use of standard off-the-shelf memory compo- nents. n the sdram controller supports programmable tim- ing options and provides the required external clock. n up to four 32-bit banks of sdram are supported with a maximum capacity of 256 mbytes. n an important reliability-enhancing error correction code (ecc) feature is built into the sdram control- ler. the resultant increase in the memory content reliability enables the lansc520 microcontroller to be effectively utilized in applications that require more reliable operation, such as communications environments. n the sdram controller contains a write buffer and read ahead buffer subsystem that improves both write and read performance. n sdram refresh options allow the sdram contents to be maintained during reset. rom/flash controller the lansc520 microcontroller provides an integrated rom controller for glueless interfacing to rom and flash devices. the lansc520 microcontroller sup- ports two types of interfaces to such devicesa simple interface via the gp bus (see easy-to-use gp bus in- terface on page 31) for 8- and 16-bit devices, and an interface to the sdram memory data bus for higher performance 8-, 16-, and 32-bit devices.
lan?sc520 microcontroller data sheet 31 preliminary the rom/flash controller: n reduces system cost by gluelessly interfacing static memory with up to three rom/flash chip se- lects n supports execute-in-place (xip) operating systems for applications that require executing out of rom or flash memory instead of dram n supports high-performance page-mode devices flexible address-mapping hardware in addition to the memory management unit (mmu) within the am5 x 86 cpu core, the lansc520 micro- controller provides 16 programmable address region (par) registers that enable flexible placement of mem- ory (sdram, rom, flash, sram, etc.) and peripher- als into the two address spaces of the am5 x 86 cpu (memory address space and i/o address space). the par hardware allows designers to flexibly configure both address spaces and place memory and/or exter- nal peripherals, as required by the application. the in- ternal memory-mapped configuration registers space can also be remapped to accommodate system re- quirements. par registers also allow control of impor- tant attributes, such as cacheability, write protection, and code execution protection for memory resources. easy-to-use gp bus interface the lansc520 microcontroller includes a simple gen- eral-purpose bus (gp bus) that provides programma- ble bus timing and allows the connection of 8/16-bit peripheral devices and memory to the lansc520 mi- crocontroller. the gp bus operates at 33 mhz, which offers good performance at a very low interface cost. the lansc520 microcontroller provides up to eight chip selects for external gp bus devices such as off- the-shelf i/o peripherals, custom asics, and sram or nvram. the gp bus interface supports programma- ble timing and dynamic bus width and cycle stretching to accommodate a wide variety of standard peripher- als, such as uarts, 10-mbit lan controller chips and serial communications controllers. up to four external dma channels provide fly-by dma transfers between peripheral devices on the gp bus and system sdram. internally, the gp bus is used to provide a complement of integrated peripherals, such as a dma controller, programmable interrupt controller, timers, and uarts, as described in integrated peripherals on page 31. these internal peripherals are designed to operate at the full clock rate of the gp bus. the internal peripher- als can also be configured to operate in pc/at-compat- ible configuration, but are generally not restricted to this configuration. the lansc520 microcontroller provides a way to view accesses to the internal peripherals on the external gp bus for debugging purposes. clock generation the lansc520 microcontroller offers user-config- urable cpu core clock speed operation at 100 or 133 mhz for different power/performance points depending on the application. not all lansc520 microcontroller devices support all cpu clock rates. the maximum supported clock rate for a device is indicated by the part number printed on the package. the clocking circuitry can be pro- grammed to run the device at higher than the rated speeds. however, if an lansc520 microcontroller is programmed to run at a higher clock speed than that for which it is rated, then erroneous operation can result, and physical damage to the device may occur. the lansc520 microcontroller includes on-chip oscilla- tors and plls, as well as most of the required pll loop filter components. the lansc520 microcontroller re- quires two standard crystals, one for 32.768 khz and one for 33 mhz. all the clocks required inside the lansc520 microcontroller are generated from these crystals. the lansc520 microcontroller also supplies the clocks for the sdram and pci bus; however, exter- nal clock buffering may be required in some systems. note: the lansc520 microcontroller supports either a 33.000-mhz or 33.333-mhz crystal. in this docu- ment, the generic term 33 mhz refers to the system clock derived from whichever 33-mhz crystal fre- quency is being used in the system. integrated peripherals the lansc520 microcontroller is a highly integrated single-chip cpu with a set of integrated peripherals that are a superset of common pc/at peripherals, plus a set of memory-mapped peripherals that enhance its usability in various applications. n a programmable interrupt controller (pic) that pro- vides the capability to prioritize 22 interrupt levels, up to 15 of these being external sources. the pic can be programmed to operate in pc/at-compati- ble mode, but also contains extended features, in- cluding support for more sources and flexible routing that allows any interrupt request to be steered to any pic input. interrupt requests can be programmed to generate either non-maskable in- terrupt (nmi) or maskable interrupt requests. n an integrated dma controller is included for trans- ferring data between sdram and gp bus peripher- als. the gp-dma controller operates in single-cycle (fly-by) mode for more efficient transfers. the gp- dma controller can be programmed for pc/at com- patibility, but also contains enhanced features: C a double buffer-chaining mode provides a more efficient software interface C extended address and transfer counts C flexible routing of dma channels
32 lan?sc520 microcontroller data sheet preliminary n three general-purpose 16-bit timers that provide flexible cascading for extension to 32-bit operation. these timers provide the ability to configure down to the resolution of four clock periods where the clock period is the 33-mhz clock. timer input and output pins provide the ability to interface with off- chip hardware. n a standard pc/at-compatible programmable inter- val timer (pit) that consists of three 16-bit timers. n a software timer that eases the task of keeping sys- tem time. it provides 1- m s resolution and can also be used for performance monitoring. n a watchdog timer to guard against runaway soft- ware. n a real-time clock (rtc) with battery backup capa- bility. the rtc also provides 114 bytes of battery- backed ram for storage of configuration parame- ters. n two integrated 16550-compatible uarts that pro- vide full handshaking capability with eight pins each. enhancements enable the uarts to operate at baud rates up to 1.152 mbits/s. the uarts can be configured to use the integrated gp bus dma controller to transfer data between the serial ports and sdram. n a synchronous serial interface (ssi) that is compat- ible with scp, spi, and microwire slave devices. the ssi interface can be configured for either full- duplex or half-duplex operation using a 4-wire or 3-wire interface. n 32 programmable i/o pins are provided. these pins are multiplexed with other peripherals and interface functions. n the lansc520 microcontroller also provides pc/ at-compatible functions for control of the a20 gate and the soft cpu reset (ports 0060h, 0064h, 0092h). jtag boundary scan test interface the lansc520 microcontroller provides a jtag test port that is compliant with ieee 1149.1 for use during board testing. system test and debug features to facilitate debugging, the lansc520 microcontroller provides observability of many portions of its internal operation, including: n a three-pin interface that can be used in either sys- tem test mode or write buffer test mode, to aid in de- termining internal bus initiators of sdram cycles, and determining when sdram data is valid on the interface. an additional mode provides observability of integrated peripheral accesses. n a nonconcurrent arbitration mode to reduce debug complexity when pci bus masters and gp bus dma initiators are also accessing sdram. n cpu cache control and dynamic core clock speed control under program control. n ability to disable write posting and read prefetching in the sdram controller to simplify tracing of sdram cycles. n notification of memory write protection and non-ex- ecutable memory region violations.
lan?sc520 microcontroller data sheet 33 preliminary applications the figures on the following pages show the lansc520 microcontroller as it might be used in sev- eral reference design applications in the data commu- nications, information appliances, and telecommunication markets. n figure 2 on page 34 shows an lansc520 micro- controller-based smart resident gateway (srg), which is a router for a home network between the wide area network (wan) (the internet) and a local area network (lan) (an intranet of computers and information appliances in the home). the srg pro- vides firewall protection of the lan from unautho- rized access through the internet. a common internet access medium is shared by all users on the lan. a variety of connections are possible for both the wan and the lan. for example, the wan connec- tion can be a v.90 modem, cable modem, isdn, adsl, or ethernet. the lan connection can be: C homepnahome phoneline networking alli- ance, an alliance with a widely endorsed home networking specification; C bluetootha computing and telecommunica- tions industry specification that describes how computing devices can easily interconnect with each other and with home and business phones and computers using a short-range wireless con- nection); C home rfa standard competing with bluetooth for the interconnection of computing devices in a lan using radio frequency; C ethernetlocal area network technology; C power linea lan using the ac power distribu- tion network in a home or business to intercon- nect devices. digital information is transmitted on a high-frequency carrier signal on top of the ac power. n figure 3 on page 35 shows an lansc520 micro- controller-based "thin client," which is the modern replacement for the traditional terminal in a remote computing paradigm. application programs run re- motely on a server, and data is warehoused on cen- trally managed disks at the "server farm." an efficient communications protocol transmits key- board and mouse commands upstream and trans- mits video bios calls downstream. the thin client renders and displays the graphics for the user. the thin client is typically connected to an ethernet lan, although a remote location can connect to a server via a wan connection such as a modem. a minimum speed of 24 kbaud is required for the com- munication protocol, unless the application is graph- ics-intensive, in which case a faster connection is required. n figure 4 on page 36 shows an lansc520 micro- controller-based digital set top box (dstb), which is a consumer client device that uses a television set as the display. common applications for the dstb are internet access, e-mail, and streaming audio and video content. the minimal system includes a connection to the wan via a modem, adsl, or cable modem; an out- put to a tv; and an infrared (ir) link to a remote control or wireless keyboard. expanded systems in- clude dvd drives and mpeg2 decoders to deliver digital video content. a hard drive may be employed to store video data for future replay. keyboard, mouse, printer, or a video camera are options that can be included. n figure 5 on page 37 shows an lansc520 micro- controller-based telephone line concentrator lo- cated in the neighborhood that converts multiple analog subscriber loops into a high-speed digitally multiplexed line for connection to the central office switching network.
3 4 l a n ? s c 5 2 0 m i c r o c o n t r o l l e r d a t a s h e e t p r e l i m i n a r y lan?sc520 microcontroller gp bus gpa25 Cgpa0 gpd15Cgpd0 control ma12Cma0 md31Cmd0 control sdram ad31Cad0 control pcnet?-home wan interface am79c978 32-khz crystal flash or rom pci bus sdram bus adsl, cable modem lan interface rj-45 33-mhz crystal rj-11 or v.90 figure 2. lan?sc520 microcontroller-based smart residential gateway reference design or rj-45 rj-11 or
lan?sc520 microcontroller data sheet 35 preliminary ad31Cad0 control lan?sc520 microcontroller gp bus control controller vga/lcd flash pci bus sdram bus am79c973/am79c975 pcnet?-fast iii super i/o ps/2 keyboard ps/2 mouse parallel serial crt/lcd ma12 Cma0 md31Cmd0 control sdram control 32-khz crystal 33-mhz crystal rj-45 lan interface figure 3. lan?sc520 microcontroller-based thin client reference design memory gpd15 Cgpd0 gpa25Cgpa0
36 lan?sc520 microcontroller data sheet preliminary flash lan?sc520 microcontroller gp bus pci bus sdram bus eide dvd or hdd control gpa1Cgpa0 gpd15Cgpd0 ma12 Cma0 md31Cmd0 control sdram ad31Cad0 control ntsc/pal vga super i/o ps/2 keyboard ps/2 mouse parallel ir control 32-khz crystal 33-mhz crystal wan interface adsl, cable modem or v.90 rj-11 figure 4. lan?sc520 microcontroller-based digital set top box reference design memory gpa25 Cgpa0 gpd15Cgpd0 control
lan?sc520 microcontroller data sheet 37 preliminary lan?sc520 microcontroller gp bus sdram bus hdlc pcm highway t1 or e1 (6x to 10x) 32-khz crystal 33-mhz crystal ma12 Cma0 md31Cmd0 control sdram control flash control figure 5. lan?sc520 microcontroller-based telephone line concentrator reference design memory islic am79r241 quad islac am79q2241 islic am79r241 islic am79r241 islic am79r241 islic am79r241 quad islac am79q2241 islic am79r241 islic am79r241 islic am79r241 t1/e1 interface ssi analog phone lines gpd15 Cgpd0 gpa25Cgpa0
38 lan?sc520 microcontroller data sheet preliminary clock generation and control the lansc520 microcontroller is designed to gener- ate all of the internal and system clocks it requires. the lansc520 microcontroller includes on-chip oscillators and plls, as well as most of the required pll loop filter components. the lansc520 microcontroller requires two standard crystals, one for 32.768 khz and one for 33 mhz. all the clocks required inside the lansc520 microcontrol- ler are generated from these crystals. output clock pins are provided for selected clocks, pro- viding up to 24 ma of sink or source current. the lansc520 microcontroller also supplies the clocks for sdram and pci bus; however, external clock buffering may be required in some systems. figure 6 shows a system block diagram of the lansc520 microcontrollers external clocks. note: the lansc520 microcontroller supports either a 33.000-mhz or 33.333-mhz crystal. in this docu- ment, the generic term "33 mhz" refers to the system clock derived from whichever 33-mhz crystal fre- quency is being used in the system. figure 6. system clock distribution block diagram sdram 66 mhz pci device pci device 33 mhz 32kxtal2 33mxtal1 33mxtal2 32kxtal1 32.768-khz 33-mhz crystal crystal [clktest] clkpciout 33 mhz clkmemout 66 mhz clkmemin clkpciin . . . programmable optional vcc_anlg lf_pll1 r1 c1 c2 lansc520 microcontroller clktimer/ note : dotted line ovals, , signify frequency groups. driver optional clock driver clock
lan?sc520 microcontroller data sheet 39 preliminary internal clocks figure 7 shows a block diagram of the lansc520 mi- crocontrollers internal clocks. the clocks are generated from two local oscillators. the 32.768-khz oscillator is used to drive pll1 (1.47456-mhz pll), which in turn drives pll2 (36.864- mhz pll). the 36.864-mhz clock is divided by 2 to produce the 18.432-mhz uart clock. it is divided by 31 to produce the 1.1892-mhz pit clock. the 33-mhz oscillator produces the 33-mhz pci and cpu clocks. the 33-mhz oscillator is also used to drive pll3 (66-mhz pll) to produce the sdram clock. figure 7. clock source block diagram 32.768-khz crystal 32.768-khz oscillator pll2 1.47456 mhz div 31 div 2 1.1892-mhz pit 18.432-mhz uart 33-mhz oscillator pll3 32.768-khz sdram refresh 33-mhz crystal 36.864 mhz lf_pll1 32.768-khz rtc notes: 1. includes the programmable interval timer (pit), general-purpose timers, watchdog timer, and the software timer. pci cpu sdram gp bus gp dma rom ssi 33 mhz 33 mhz 33 mhz 33 mhz 33 mhz 33 mhz 66 mhz pll1 timers 1 33 mhz
40 lan?sc520 microcontroller data sheet preliminary clock specifications pll period jitter specifications are summarized in table 3. jitter specifications are only guaranteed when analog supply noise restrictions are met. table 4 shows pll lock times and oscillator start-up times. table 5 shows the oscillator input specifications. loop filter components for the 1.47456-mhz pll (pll1) must be supplied externally. they are connected be- tween the analog v cc (vcc_anlg) and the lansc520 microcontroller pin, lf_pll1. specifications for vcc_anlg are shown in table 6. figure 6 on page 38 shows the loop filter circuit composed of c1, c2, and r1. component values are given in table 7 on page 41. clock pin loading the lansc520 microcontrollers clock driver pins are designed to source or sink 24 ma. as shown in figure 6 on page 38, an external clock driver may be necessary when the system presents a large capaci- tive load. clock pads are designed to either source or sink 24 ma. the maximum amount of capacitive load that can be placed on a clock pad is determined by the required rise/fall times. use the following equation to determine the maximum capacitive loading. c = i/(dv/dt) where i = current, dv = voltage change, and dt = time change. as an example, suppose that the system requires a rise/fall time of 1 ns, with a voltage swing of 2.5 v. then, the maximum capacitive load is: c max = 24 ma/(2.5 v/1 ns) = 9.6 pf table 3. clock jitter specifications clock name clock frequency min nominal max pit 1.1892 mhz 828.3 ns 840.9 ns 853.5 ns uart 18.432 mhz 53.44 ns 54.25 ns 55.07 ns cpu 33.000 mhz or 33.333 mhz 250 ps sdram 66.000 mhz or 66.666 mhz 14.775 ns 15.0 ns 15.225 ns table 4. clock startup and lock times clock source min typ max 32.768-khz oscillator 1 s 33-mhz oscillator 10 ms pll1 (1.47456 mhz) 10 ms pll2 (36.864 mhz) 100 m s pll3 (66 mhz) 50 m s table 5. oscillator input specifications parameter min typ max 32kxtal2 input voltage low C0.3 v +0.8 v 32kxtal2 input voltage high vcc_rtc C 0.8 v vcc_rtc + 0.3 v 33mxtal2 input voltage low C0.3 v +0.8 v 33mxtal2 input voltage high vcc_anlg C 0.8 v vcc_anlg + 0.3 v table 6. analog vcc (vcc_anlg) specifications parameter min typ max peak-to-peak noise on vcc_anlg 75 mv vcc_anlg voltage level 2.25 v 2.5 v 2.75 v vcc_anlg current 1.4 ma 1.9 ma 2.1 ma
lan?sc520 microcontroller data sheet 41 preliminary selecting a crystal the accuracy of the rtc depends on several factors relating to crystal selection and board design. a clock timing budget determines the clock accuracy. the de- signer should determine the timing budget before se- lecting a crystal. there are four major contributors to a clock timing budget. n frequency tolerance this is the crystal calibration frequency. it states how far off the actual crystal frequency is from the nominal frequency. for a typical 32.768-khz crystal (watch crystal), the frequency tolerance is 20 parts per million (ppm). frequency tolerance is specified at room temperature. n frequency stability this parameter is a measure of how much the crystal resonant frequency is influenced by operating temperature. for watch crystals, typical numbers are around C30 ppm over the temperature range. n aging this parameter is how much the crystal resonant frequency changes with time. typical aging numbers are 3 ppm per year. n load capacitance the crystal is calibrated with a specific load capacitance. if the system load capacitance does not equal the crystal load capacitance, a timing error is introduced. the timing error is calculated by the following equation. error = {[1 + c1/(cl xtal +co)] 1/2 C [1 +c1/ (cl system +co)] 1/2 }/ [1 + c1/(cl xtal +co)] 1/2 if you multiply error by 10 6 , the error in ppm is given. in the above equation, c1 is the crystal motional capacitance, and co is the crystal static capacitance. cl xtal is the crystal load capacitance, and cl system is the system load capacitance. once the complete timing error has been calculated by adding all of the errors together, compare it to the initial timing budget. table 8 provides a convenient translation of ppm to seconds per month. 32.768-khz crystal selection the 32.768-khz crystal oscillator is shown in figure 8. the oscillator load capacitance is 5 pf. table 9 pro- vides specifications for selecting a proper 32.768-khz crystal. the ecliptek ecpsm29t is recommended. figure 8. 32.768-khz crystal circuit table 7. pll1 loop filter components parameter min typ max c1 0.009 m f0.01 m f0.011 m f c2 0.0009 m f0.001 m f 0.0011 m f r1 4.465 k w 4.7 k w 4.935 k w table 8. timing error as it translates to clock accuracy timing error (parts per million) seconds/month 10 25.9 20 51.8 30 77.8 40 103.7 50 129.6 10 pf 10 pf 32.768-khz crystal internal external amp 32kxtal1 32kxtal2
42 lan?sc520 microcontroller data sheet preliminary 33-mhz crystal selection the same information related to the 32.768-khz crystal selection applies to the 33-mhz crystal selection. the lansc520 microcontroller supports either a 33.000- mhz or 33.333-mhz crystal. specifications for the 33-mhz crystal are shown in table 10. amd recommends using a fundamental mode 33.333- mhz crystal. if a third overtone crystal is used, the os- cillator gain may not be large enough to produce a reli- able clock. third overtone crystal component selection for the third overtone crystal circuit implementation, refer to figure 9 on page 43. components c4 and l1 are selected by the user. c3 is a parasitic capacitor composed of board parasitics. typical values for c3 range from 5 pf to 15 pf. c4 is required for dc isolation. a nominal value for c4 is 0.1 m f. l1 in conjunction with c3 and c2 form a resonant cir- cuit. the value of l3 is selected so that the resonant frequency is between the fundamental frequency and the third overtone frequency. for a 33.333-mhz third overtone crystal, the fundamental frequency is 11.111 mhz. from this, a desirable resonant frequency is be- tween 11.111 mhz and 33.333 mhz. a good target fre- quency is 22.222 mhz. l1 is selected from the basic equation: l1 = 1/[(2 ? pi ? frequency) 2 ? (c2 + c3)] assuming that the board parasitics are 15 pf, then: l1 = 1/[ (2 ? pi ? 22.222 mhz) 2 ? (7 pf + 15 pf)] = 2.3 m h table 9. 32.768-khz crystal specifications parameter min typ max comment nominal frequency 32.768 khz effective series resistance (esr) 60000 w drive level 1 m w load capacitance (lansc520 microcontroller) 4.5 pf 5 pf 5.5 pf resonant mode parallel crystal cut bt operating mode fundamental table 10. 33-mhz crystal specifications parameter or characteristic min typ max comment nominal frequency 33.000 mhz 33.333 mhz esr 40 w drive level 1 mw load capacitance (lansc520 microcontroller) 2.5 pf resonant mode parallel crystal cut at or bt operating mode fundamental
lan?sc520 microcontroller data sheet 43 preliminary figure 9. 33.333-mhz third overtone crystal implementation running the lan?sc520 microcontroller at 33.333 mhz the clock that is supplied to the pci bus (clkpciout) is exactly the same as the frequency of the crystal. the lansc520 microcontroller simply buffers the 33-mhz crystal input and provides it to the clkpciout pin. since crystals have inaccuracies, it is possible that these inaccuracies cause the period of clkpciout to become marginally less than 30 ns. it is up to the system designer to choose the accuracy of the crystal used with the lansc520 microcontroller. the 33.000-mhz frequency provides a better guard band than the 33.333-mhz crystal. in practice, most pci devices can tolerate both frequencies, but it is im- portant to be aware of the impact of choosing the crys- tal on this potential violation of the pci bus specifications. the pci bus specification requires that the minimum clock period be 30 ns. internal external amp 33mxtal1 33mxtal2 c4 = 0.1 m f l1 c3 c1 =7 pf c2 = 7 pf
44 lan?sc520 microcontroller data sheet preliminary bypassing internal oscillators the 32.768-khz and the 33-mhz lansc520 micro- controller oscillators can be bypassed by connecting an external clock to the crystal pins. refer to figure 10 and figure 11 for the suggested circuitry. figure 10. bypassing the 32.768-khz oscillator figure 11. bypassing the 33-mhz oscillator 32kxtal2 32kxtal1 100 k w lansc520 microcontroller 2.5 v 10% typical external 32.768-khz oscillator r2 r1 note: r1 and r2 are required when the external oscillator voltage, v osc , exceeds 2.5 v. the value of r1 depends on v osc according to the formula r1 = 100 k w (v osc C 2.5) / 2.5, where 100 k w is the fixed value of r2, and 2.5 is the typical voltage for 32kxtal2 ( 10%) . no connect 33mxtal2 33mxtal1 lansc520 microcontroller 2.5-v 10% typical external 33-mhz oscillator
lan?sc520 microcontroller data sheet 45 preliminary figure 12. rtc voltage monitor block diagram rtc voltage monitor if an external backup battery is connected to the lansc520 microcontrollers vcc_rtc pin, the real- time clock (rtc) remains operational even if all the other power supplies are turned off. the lansc520 microcontrollers rtc voltage monitor is designed to signal the rtc core when the backup battery is not in- stalled or is low. additionally, the voltage monitor circuit signals the rtc core when the rest of the system is being powered down. features of the voltage monitor include: n bandgap voltage generator for precision reference voltage n high-gain amplifier for adjusting bandgap voltage to low battery trip voltage n the rtc can be connected to the main power plane if a backup battery is not needed in the system. figure 12 shows a block diagram of the rtc voltage monitor. the voltage monitor circuit uses a delta vbe voltage (voltage from base to emitter) source to generate a bandgap voltage of approximately 1.23 v. this voltage is the input to an amplifier whose gain is such that the output voltage is a 2-v reference. this reference signal is an input to a comparator, along with the backup bat- tery voltage, bbatsen. if bbatsen drops below the 2-v reference, an rtc invalidate signal is generated to notify the user via the rtc_vrt bit (rtc index 0dh[7]) that the rtc contents are no longer valid. there are three conditions that trigger an rtc invalida- tion. they are the following: n bbatsen drops below 2 v (sampled when pwr- good asserts)during operation from the main power supply, the backup battery voltage might drop below the trip voltage (2 v). the rtc is not in- validated until a pwrgood assertion occurs. n power is applied to vcc_rtc (the backup battery is plugged in)when the backup battery is plugged in, the rtc is immediately invalidated. n no battery during power-up (sampled after pwr- good asserts)if the system does not contain a backup battery and the bbatsen line potential is below 2 v, the rtc is invalidated when pwrgood asserts. in addition to the backup battery monitor function, the voltage monitor also provides a power-down signal to the rtc. this signal is used to isolate the rtc core from the rest of the integrated peripherals. a timing diagram for this sequence is shown in figure 27 on page 60. + C bandgap vbg amplifier bbatsen one- shot rtc reset flip- flop d ck q pwrgood 32 khz internal rtc power-down 2.0 v voltage generator
46 lan?sc520 microcontroller data sheet preliminary backup battery considerations the behavior of the rtc when the primary power sup- ply is turned off depends on whether or not an external backup battery is included in the system design. using an external rtc backup battery an implementation using a backup battery is shown in figure 13 on page 47. the primary power source for vcc_rtc is the main power plane (vcc). d1 should be chosen so that the forward voltage drop is small, less than 0.25 v. d1 also prevents the backup battery from powering up the vcc power plane when the main sup- ply is turned off. the backup battery voltage must not exceed 3.3 v (af- fects the bbatsen and vcc_rtc pins); higher volt- ages may damage the lansc520 microcontroller. the rc network composed of r1 and c2 provides a time delay for the internal circuit power-up sequence. accuracy tolerances are 10% of nominal values given in table 11. c1 is for high-frequency filtering purposes. not using an external rtc backup battery for the system that is not using a backup battery, figure 14 on page 47 shows how the circuit should be designed. it uses the same rc that is needed by the battery system, but it is now connected to vcc_rtc. for this configuration, the rtc is invalidated after power-up, but is not invalidated by subsequent pwr- good assertions. n the rtc is invalidated after a power-up. in this case, power has been removed from the rtc, so it should be invalidated. n when a reset switch tied to pwrgood is pressed (v cc remains high), pwrgood reasserts with bbatsen high, so the rtc is not invalidated. in this case, power did not go away, so the rtc con- tents are still good. vcc_anlg is selected as the power plane for vcc_rtc because it is a well-filtered power plane that is well below the vcc_rtc maximum of 3.3 v. component values for the resistor and capacitor are shown in table 11. table 11. rtc voltage monitor component specifications component parameter min nominal max d1 forward voltage drop 0.25 v d2 forward voltage drop note 1 d1, d2 forward current 100 m a c1 capacitance 5 pf 10 pf 20 pf c2 capacitance 180 pf 200 pf 400 pf r1 resistance 900 1 k w 1.1 k w notes: 1. diode should be selected so that the voltage into the rtc power pin (vcc_rtc) does not exceed 3.3 v.
lan?sc520 microcontroller data sheet 47 preliminary figure 13. circuit with backup battery figure 14. circuit without backup battery batt vcc_rtc vcc_rtc bbatsen c1 d1 d2 r1 c2 (3.3 v max) 10 w lansc520 microcontroller vcc_anlg c1 r1 c2 lansc520 microcontroller vcc_rtc bbatsen
48 lan?sc520 microcontroller data sheet preliminary absolute maximum ratings 1 notes: 1. warningthe absolute maximum ratings are stress ratings only. stresses above those listed can cause permanent dam- age. operation beyond the values specified in operating ranges at commercial temperatures is not recommended, and ex- tended exposure beyond these operating range values can affect device reliability. symbol parameter minimum maximum unit storage temperature C65 +125 c vcc_core core voltage 2 2. referenced from gnd. C0.5 3.2 v vcc_i/o i/o voltage 2,3 3. all inputs are 5-v tolerant. C0.5 5.5 v vcc_rtc real-time clock voltage 2 C0.5 4.5 v vcc_anlg analog voltage 2 C0.5 3.2 v operating ranges at commercial temperatures 1 notes: 1. operating ranges define the temperature and voltage limits between which the functionality of the device is guaranteed. symbol parameter description minimum typical maximum unit t case commercial case temperature operating in free air 0 +85 c vcc_core core voltage 2 2. referenced from gnd. +2.375 +2.5 +2.625 v vcc_i/o i/o voltage 2,3 3. all inputs are 5-v tolerant. +3.0 +3.3 +3.6 v vcc_rtc real-time clock voltage 2 +2.0 +2.5 +3.3 v vcc_anlg analog voltage 2 +2.25 +2.5 +2.75 v
lan?sc520 microcontroller data sheet 49 preliminary voltage levels for pci interface pins the voltage characteristics of the pci interface input pins are specified in the pci local bus specification, revision 2.2, section 4.2.1 5v signaling environment and section 4.2.2 3.3v signaling environment. the voltage characteristics of the pci interface output pins are specified in the pci local bus specification, revision 2.2, 4.2.2 3.3v signaling environment. voltage levels for non-pci interface pins 1 notes: 1. the drive strengths of all the pins are listed in table 20, pin list summary, on page a-7. the pins with variable drive strengths can take on the characteristics of 12-, 18-, or 24-ma signals. advance information unit symbol parameter description min max v il input low voltage C 0.3 + 0.8 v v ih input high voltage 2.0 vcc_i/o + 1.7 v v oh1 output high voltage (i oh = C6 ma) vcc_i/o C 0.45 v v ol1 output low voltage (i ol = 6 ma) 0.45 v v oh2 output high voltage (i oh = C12 ma) vcc_i/o C 0.45 v v ol2 output low voltage (i ol = 12 ma) 0.45 v v oh3 output high voltage (i oh = C18 ma) vcc_i/o C 0.45 v v ol3 output low voltage (i ol = 18 ma) 0.45 v v oh4 output high voltage (i oh = C24 ma) vcc_i/o C 0.45 v v ol4 output low voltage (i ol = 24 ma) 0.45 v
50 lan?sc520 microcontroller data sheet preliminary dc characteristics over commercial operating ranges notes advance information unit symbol parameter description min typ max i cc _core current for vcc_core supply @ 133 mhz 465 660 ma i cc _core current for vcc_core supply @ 100 mhz 380 540 ma i cc _i/o current for vcc_ i/o supply @ 33-mhz 1 notes: 1. estimate based on 3.3-v operation. current for the i/o supply is constant, independent of the cpu frequency. 100 120 ma i cc _rtc current for rtc-only mode 2,3 2. value determined by simulation will be updated once characterization is complete. 3. current measured with power applied only to the vcc_rtc supplies. 5 m a i cc _anlg current for anlg-only mode 1.4 1.9 2.1 ma i li1 input leakage current (0.1 v < v in < vcc_i/o) (all pins except those with internal pullup or pulldown resistors) 4,5 4. vcc_i/o = 3.6 v. 5. table 20, pin list summary, on page a-7 shows which pins have internal pullups or pulldowns. ? 20 m a i li2 input leakage current v in = (vcc_i/o C 0.1 v) (all pins with internal pulldown resistors) 4, 5 60 m a i li3 input leakage current v in = 0.1 v (all pins with internal pullup resistors) 5 C60 m a i lo output leakage current 15 m a
lan?sc520 microcontroller data sheet 51 preliminary capacitance pci interface pin capacitance pin capacitance values are specified in the pci local bus specification , revision 2.2, section 4.2.2.1 dc specifications, table 4-3: dc specifications for 3.3v signaling. crystal capacitance the crystal specifications can be found in table 9, 32.768-khz crystal specifications on page 42 and table 10, 33-mhz crystal specifications on page 42. derating curves all programmable i/o pins can be driven to the maxi- mum drive current at once. the derating curves on the following pages can be used to determine potential specified timing variations based on system capacitive loading. table 20, pin list summary, on page a-7 has a column named max load (pf). this column describes the specification load presented to the specific pin, when testing was performed, to generate the timing specification docu- mented in the ac characteristics section of this data sheet. if the capacitive load on gpa0 is 70 pf, then a typical rise time is 6.5 ns. from figure 18, the same load gives a typical fall time of 7 ns. non-pci interface pin capacitance advance information unit symbol parameter description test conditions min max c in input capacitance f c =1 mhz 10 pf c 32kxtal 32kxtal1, 33kxtal2 pin capacitance 20 pf c 33mxtal 33mxtal1, 33mxtal2 pin capacitance 15 pf c out output capacitance 10 pf c io i/o pin capacitance 10 pf
52 lan?sc520 microcontroller data sheet preliminary figure 15. i/o drive 6-ma rise time figure 16. i/o drive 6-ma fall time 0 5 10 15 20 25 30 35 0 20 40 60 80 100 120 pf ns worst case typical 0 5 10 15 20 25 30 35 pf ns worst case typical
lan?sc520 microcontroller data sheet 53 preliminary figure 17. i/o drive 12-ma rise time figure 18. i/o drive 12-ma fall time 0 2 4 6 8 10 12 14 16 18 0 20 40 60 80 100 120 pf ns worst case typical 0 2 4 6 8 10 12 14 16 18 0 20 40 60 80 100 120 pf ns worst case typical
54 lan?sc520 microcontroller data sheet preliminary figure 19. i/o drive 24-ma rise time figure 20. i/o drive 24-ma fall time 0 1 2 3 4 5 6 7 8 9 0 20 40 60 80 100 120 pf ns worst case typical 0 1 2 3 4 5 6 7 8 9 0 20 40 60 80 100 120 pf ns worst case typical
lan?sc520 microcontroller data sheet 55 preliminary figure 21. pci pads rise time with 1-ns rise/fall figure 22. pci pads fall time with 1-ns rise/fall 0 1 2 3 4 5 6 7 0 102030405060 pf ns worst case typical best case 0 0.5 1 1.5 2 2.5 3 3.5 4 0 102030405060 pf ns best case worst case typical
56 lan?sc520 microcontroller data sheet preliminary power characteristics dynamic i cc measurements are dependent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the outputs. actual power supply current is dependent on system design and may be greater or less than the typical i cc number present here. maximum power is measured at maxi- mum v cc at maximum case temperature. typical power is measured at typical v cc at 55c. for power dissipation values, refer to table 12 and table 13. thermal characteristics 388-pin pbga package the lansc520 microcontroller is specified for opera- tion with case temperature ranges from 0 ? c to +85 ? c for vcc_core = 2.5 v 10% and vcc_i/o = 3.3 v 10%. case temperature is measured at the top center of the package as shown in figure 23. the various temperatures and thermal resistances can be deter- mined using the equations in figure 24 with informa- tion given in table 15. thermal, electrical, and mechanical characteristics of amd qualified packages (including the 388 pbga) can be found on amds website at www.amd.com. click on the link products, and then click on the document link packages and packing methodologies. figure 23. thermal resistance ( ? c/watt) table 12. device power dissipation 1 notes: 1. device power dissipation calculation assumes that 50% of the i/o power is consumed on chip. power 100 mhz 133 mhz unit maximum power 1.7 2.0 w typical power 1.2 1.4 w table 13. vcc_anlg and vcc_rtc power dissipation supply typical max unit vcc_anlg voltage level 2.5 2.75 v vcc_anlg current 1.9 2.1 ma vcc_anlg power 4.75 5.78 mw vcc_rtc voltage level 2.5 3.3 v vcc_rtc current 5 m a vcc_rtc power 12.5 m w q ja q ca q jc q ja = q jc + q ca t c
lan?sc520 microcontroller data sheet 57 preliminary table 14. thermal resistance (c/w) q jc and q ja for bga package with 6-layer board board type 1 notes: 1. the board type is described in the jedec standards document entitled thermal test chip guideline (wire bond type chip) at www.jedec.org. on the home page click on the link free standards and docs, and then click on the document link jesd51-4 under jedec publications. q jc q ja vs. airflow 0 200 400 600 800 6-layer 3.3 16.6 14.7 13.6 12.9 12.5 table 15. maximum t a for plastic bga package with 6-layer board 1 with t case = 85c notes: 1. the board type is described in the jedec standards document entitled thermal test chip guideline (wire bond type chip) at www.jedec.org. on the home page click on the link free standards and docs, and then click on the document link jesd51-4 under jedec publications. cpu clock rate airflow (linear feet per minute) 0 200 400 600 800 133 mhz 67c 70c 71c 72c 73c 100 mhz 70c 72c 74c 74c 75c q ja = q jc + q ca p = i cc ? v cc t j = t c + (p ? q jc ) t j = t a + (p ? q ja ) where: q ja = thermal resistance from junction to ambient q jc = thermal resistance from junction to case q ca = thermal resistance from case to ambient t j = junction temperature t a = ambient temperature t c = case temperature p = power in watts i cc = power supply current in ma figure 24. thermal characteristics equations
58 lan?sc520 microcontroller data sheet preliminary switching characteristics and waveforms the ac switching specifications provided in the ac characteristics tables that follow consist of output de- lays, input setup requirements, and input hold require- ments. ac specifications measurement is defined by the fig- ures that follow each timing table. all timings are refer- enced to 1.5 v unless otherwise specified. output delays are specified with minimum and maxi- mum limits, measured as shown. the minimum delay times are hold times provided to external circuitry. input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. within the sampling window, a synchronous input sig- nal must be stable for correct microcontroller operation. ac switching test waveforms non-pci bus interface pins figure 25. ac switching test waveforms pci bus interface pins for ac timing for pci bus interface pins, refer to the pci local bus specification , revision 2.2, 4.2.3.3 measurement and test conditions, figure 4-7: output timing measurement conditions, and figure 4-8: input timing measurement conditions. key to switching waveforms waveforms inputs outputs must be steady will be steady may change from h to l will be changing from h to l may change from l to h will be changing from l to h dont care, any change permitted changing, state unknown does not apply center line is high-impedance off state vcc_i/o ? 2 vcc_i/o ? 2 v ih = vcc_i/o input v il = 0 test points output note: for ac testing, inputs are driven at 3 v for a logic 1 and 0 v for a logic 0.
lan?sc520 microcontroller data sheet 59 preliminary switching characteristics over commercial operating ranges in this section, the following timings and timing wave- forms are shown: n power-on reset (page 59) n reset (page 61) n rom (page 63) n pci bus (page 65) n sdram (page 66) n sdram clock (page 68) n gp bus (page 69) n gp bus dma read (page 71) n gp bus dma write (page 72) n ssi (page 73) n jtag (page 74) power-on reset timing symbol parameter description notes advance information unit min typ max t1 vcc_rtc valid hold before all other v cc s are valid 0 t2 pwrgood valid hold from all v cc valid (except vcc_rtc) 1 1s t3 vcc_rtc valid to bbatsen active 2 100 m s t4 cfgx, rstldx, debug_enter, inst_trce, amdebug_dis setup to pwrgood active 5ns t5 cfgx, rstldx, debug_enter, inst_trce, amdebug_dis hold from pwrgood active 5ns t6 gpreset active from pwrgood inactive 10 11 ms t7 rst active from pwrgood inactive 10 11 ms t8 pwrgood inactive to all v cc s invalid (except vcc_rtc) 3 33 m s notes: 1. this parameter is dependent on the 32-khz oscillator startup time, which is dependent on the characteristics of the crystal, leakage and capacitive coupling on the board, and ambient temperature. 2. this parameter ensures that the internal rtc valid status bit is cleared to indicate that the rtc time and cmos contents are invalid. 3. this parameter must be met to ensure that the rtc date and time are not invalidated.
60 lan?sc520 microcontroller data sheet preliminary figure 26. power-up timing sequence figure 27. pwrgood timing for rtc standalone mode t4 t5 t1 t2 t3 t6 t7 vcc_rtc all other v cc s pwrgood cfgx, rstldx, bbatsen gpreset rst debug_enter, inst_trce, amdebug_dis pwrgood vcc 1 32 khz 2.5 v 2.0 v t8 notes: 2. applies to all v cc s except for vcc_rtc, which is left on for this mode. 3. these timings apply only when powering down the chip while leaving only the rtc powered. 4. guarantees at least one rising edge on the 32-khz signal after reset before 2 v is reached.
lan?sc520 microcontroller data sheet 61 preliminary figure 28. external system reset timing with power applied reset timing with power applied symbol parameter description notes advance information unit min max t1 pwrgood inactive pulse width 20 ns t2 cfgx, rstldx setup to pwrgood active 5 ns t3 cfgx, rstldx hold from pwrgood active 5 ns t4 pwrgood inactive to gpreset, rst outputs active 20 ns t5 pwrgood active to gpreset, rst outputs inactive 10 ms t6 prgreset active pulse width 40 ns t7 prgreset active to gpreset, rst outputs active 90 1000 ns t8 prgreset inactive to gpreset, rst outputs inactive 10 ms t9 reset outputs (gpreset, rst ) active pulse width for internally generated system reset 1 notes: 1. internal system reset sources include software system reset (sys_rst bit), amdebug interface system reset, and watchdog timer reset. 10 11 ms t2 t3 t1 t4 t5 t4 t5 pwrgood cfgx, rstldx gpreset rst
62 lan?sc520 microcontroller data sheet preliminary figure 29. prgreset timing figure 30. internal system reset timing t6 t7 t8 t7 t8 prgreset gpreset rst t9 t9 gpreset rst
lan?sc520 microcontroller data sheet 63 preliminary rom timing symbol parameter description 1 notes advance information unit min max t1 gpa25Cgpa4, chip select setup before rombufoe , romrd , gpa3Cgpa0 active 10 ns t2 gpa25Cgpa4, chip select active pulse-width read access 2 (p fws + 1) ? 30 3 ns t3 read data valid required from gpa3Cgpa0, romrd and rombufoe , non-page-mode access 2 ((p fws + 1) ? 30 3 ) C 20 ns t4 read data valid from gpa3Cgpa0, page-mode access 4 ((p sws + 1) ? 30 3 ) C 20 ns t5 read data hold from address, chip select, romrd , and rombufoe 0ns t6 gpa25Cgpa0, chip select hold time from rombufoe , romrd read access 0ns t7 rombufoe , romrd read recovery time 25 ns t8 gpa3Cgpa0 valid, first access 2 ((p fws + 1) ? 30 3 ) C 5 ns t9 gpa3Cgpa0 valid time, non-page-mode access 2 ((p fws + 1) ? 30 3 ) C 5 ns t10 gpa3Cgpa0 valid time, page-mode access 4 ((p sws + 1) ? 30 3 ) C 5 ns t11 gpa25Cgpa0, chip select setup to rombufoe , flashwr active 25 ns t12 gpa25Cgpa0 valid, chip select active pulse-width write access 2 (p fws + 2) ? 30 3 ns t13 write data valid setup to rombufoe , flashwr 15 ns t14 gpa25Cgpa0, chip select hold time from rombufoe , flashwr write access 15 ns t15 write data hold time from rombufoe , flashwr write access 15 ns t16 rombufoe , flashwr write recovery time 45 ns notes: 1. chip select includes bootcs , romcs1 , and romcs2 . 2. p fws represents the programmable first wait state timing parameter in the rom controller register for the corresponding rom chip select. 3. the value of 30 corresponds to the 33-mhz crystal frequency and assumes 33.333 mhz. 4. p sws represents the programmable subsequent wait state timing parameter in the rom controller register for the correspond- ing rom chip select.
64 lan?sc520 microcontroller data sheet preliminary figure 31. non-burst rom read cycle timing figure 32. page-mode rom read cycle timing t2 t9 t7 t7 t6 t8 t1 t1 t3 t5 t3 t5 t3 t5 gpa3Cgpa0 rombufoe romrd gpa25Cgpa4, chip select notes: 1. chip select includes bootcs , romcs1 , and romcs2 . 2. data includes gpd15Cgpd0 or md31Cmd0. data (in) t2 t10 t7 t7 t6 t8 t1 t1 t3 t5 t4 t5 t4 t5 gpa3Cgpa0 rombufoe romrd notes: 1. chip select includes bootcs , romcs1 , and romcs2 . 2. data includes gpd15Cgpd0 or md31Cmd0. data (in) gpa25Cgpa4, chip select
lan?sc520 microcontroller data sheet 65 preliminary figure 33. flash write cycle timing pci bus timing the characteristics of the pci interface pins are speci- fied in the pci local bus specification , revision 2.2, section 4.2.1.1 dc specifications, table 4-1: dc spec- ifications for 5v signaling, and section 4.2.2.1 dc specifications, table 4-3: dc specifications for 3.3v signaling. t12 t16 t13 t16 t14 t11 t11 t15 rombufoe flashwr gpa25Cgpa0, chip select data (out) notes: 1. chip select includes bootcs , romcs1 , and romcs2 . 2. data includes gpd15Cgpd0 or md31Cmd0.
66 lan?sc520 microcontroller data sheet preliminary sdram timing symbol parameter name parameter description notes advance information unit min max t1 t rc refresh active to active command period t rc 135 1 notes: 1. corresponds to the 33-mhz crystal frequency and assumes 33.333 mhz with no guardband. ns t2 t ras active command to precharge command period t ras 75 1 7500 ns t3 t rcd active command to column command same bank t rcd 30 1 ns t4 t rp precharge command to active command period t rp 30 1 ns t5 t dpl write recovery or data-in to precharge lead time t dpl 30 1 ns t6 t ckh ck high pulse width t ckh 7ns t7 t ckl ck low pulse width t ckl 7ns t8 t ck ck period t ck 15 1 ns t9 t cs command setup t cs 5ns t10 t ch command hold t ch 2ns t11 t ac access time from ck t ac 2 2. this access time is based on the clock period assuming minimal delay between the clkmemout output and the clkmemin input. it does not take into account external delays for clock buffering/skew, clock loading/routing, and data loading/routing. the delays that the system designer must take into consideration are identified by the equation below: t ac + t skew + t ck_ld + t d_ld <= t ck where: t ac = access time of sdram device (not impacted by board design) t skew = delay between clkmemout to clkmemin t ck_ld = additional clock delay due to loading t d_ld = data delay due to loading t ck = sdram memory clock = 15 ns (assumes 33.333 mhz crystal) 12 ns t12 t dh data-in (read) hold time t dh 2ns t13 t hz ck to data-out high-impedance t hz 15 ns t14 t lz ck to data-out low-impedance t lz 0ns t15 t t transition time of ck, rise and fall t t 1ns t16 t ds data-out (write) setup time t ds 3ns t17 t dh data-out hold time t dh 2ns t18 t as address setup time t as 5ns t19 t ah address hold time t ah 2ns
lan?sc520 microcontroller data sheet 67 preliminary figure 34. sdram write and read timing data column t2 clkmemin ma md 4 cmd 1 bank row bank column row column t18 t5 t19 t3 t9 t4 write prechrg active prechrg 2 write active read t10 t13 t14 t16 data out data in t11 3 t12 notes: 1. cmd applies to sras, scas, ba0, ba1, swe, scsx, and sdqm. 2. prechrg is an abbreviation for precharge. 3. t11 is shown for cas latency = 2. 4. md includes all sdram data lines and all mecc lines. 5. parameter t1 (t rc ) is not shown. t17 write precharge row active precharge row active write read t6 t7 t8 t15
68 lan?sc520 microcontroller data sheet preliminary figure 35. sdram clock timing sdram clock timing symbol parameter description notes advance information unit min max t1 clkmemout period 1 notes: 1. this parameter is based on a pll, 2x multiplier of the frequency of the 33-mhz crystal. the value is affected by the chosen frequency of the crystal (33.000 mhz or 33.333 mhz). 14 ns t2 clkmemout high time 1 7ns t3 clkmemout low time 1 7ns t4 clkmemin delay rising from clkmemout rising C0.5 6 ns t4 t1 t2 t3 clkmemout clkmemin
lan?sc520 microcontroller data sheet 69 preliminary gp bus timing 1 notes: 1. if the gpcs7 Cgpcs0 signals are internally qualified with the command, the gpcs7 Cgpcs0 and command pads switch simultaneously. gpcsx may deassert prior to the deassertion of the command. symbol parameter description notes advance information unit min max t1 setup, gpa, gpbhe stable to command assertion, 8/16-bit i/o and memory access 2 2. offs represents the programmable offset timing parameter for the corresponding pin. ((offs+1) ? 30 3 ) C 5 3. the 30 corresponds to the 33-mhz crystal frequency and assumes 33.333 mhz. ns t2 setup, gpiocs16 , gpmemcs16 asserted to programmed command deassertion 45 ns t2a delay, gpiocs16 , gpmemcs16 hold from programmed command deassertion 0ns t3 command pulse width, gpiowr , gpmemwr , gpiord , gpiowr , 8/16-bit cycles 4 4. pw represents the programmable pulse width parameter for the corresponding pin. ((pw + 1) ? 30 3 ) C 5 ns t4 gpa, gpbhe hold from command deassertion 5 5. this can be increased based on the programmed chip-select offset and pulse width along with its recovery time. 25 ns t5 setup, gprdy deasserted to programmed command deassertion 6 6. this parameter must be met to ensure that a cycle is extended by gprdy. 45 ns t6 gprdy pulse width 6 30 3 ns t7 command high (deassertion) time 85 ns t11 setup, gpd to write command assertion ((offs+1) ? 30 3 ) C 15 ns t12 hold, gpd from write command deassertion 25 ns t13 setup, gpd stable to read command deassertion 10 ns t14 hold, gpd from read command deassertion 0 ns t15 setup, gpa, gpbhe stable to gpale falling edge 2,4 (offs + pw+2) ? 30 3 C 10 ns t16 gpale pulse width 4 ((pw + 1) ? 30 3 ) C 5 ns t17 setup, gpaen low to gpiord /gpiowr assertion (echo mode) ((offs+1) ? 30 3 ) C 15 ns t20 7 7. this parameter assumes that the gpcs7 Cgpcs0 signals are not internally qualified with the command. setup, gpa, gpbhe stable to gpcs 2 (offs+1) ? 30 3 C 5 ns t21 7 hold, gpa, gpbhe stable from gpcs 8 8. rcov represents the programmable recovery time for the chip selects. (rcov+1) ? 30 3 C 5 ns t22 7 pulse width, gpcs 4 ((pw + 1) ? 30 3 ) C 5 ns t27 hold, gpaen to gpiord /gpiowr deassertion (echo mode) 5 25 ns t45 setup, gpdbufoe assertion to command assertion ((offs+1) ? 30 3 ) C 15 ns t46 hold, gpdbufoe assertion from command assertion 5 25 ns
70 lan?sc520 microcontroller data sheet preliminary figure 36. gp bus non-dma cycle timing t20 t22 t21 t22 t20 t22 t21 t22 t16 t15 t16 t15 t1 t3 t4 t1 t3 t4 t7 t7 t2 t2a t5 t6 t t5 t11 t12 t13 t14 t45 t46 t45 t46 t17 t27 t17 t27 gpa25Cgpa0, gpbhe gpcs7 Cgpcs0 gpale gpiowr /gpmemwr gpiord /gpmemrd gpiocs16 /gpmemcs16 gprdy gpd15Cgpd0 (write) gpd15Cgpd0 (read) gpdbufoe gpaen t2 t6
lan?sc520 microcontroller data sheet 71 preliminary figure 37. gp-dma read cycle timing gp bus dma read cycle timing symbol parameter description advance information unit min max t clk gp-dma clock cycle 58 244 ns t1 gpdrq asserted to gpdack assertion 2 t clk t2 gpdack asserted to gpaen and gpdbufoe assertion 1 t clk t3 gpd setup time for gpiowr , gpmemwr for non-compressed and non-extended write mode 20 ns t4 gpdack asserted to gpiowr , gpmemwr assertion 3.5 t clk t5 gpiowr , gpmemwr pulse width 1 t clk t6 gpdack asserted to gptc assertion 3.5 t clk t7 gptc pulse width 1.5 t clk t8 gpaen and gpdbufoe deasserted from command deasserted 1 t clk t9 gpdrq deasserted from gpdack assertion 0 ns t10 gpdack deasserted from command deasserted 1 t clk t11 gpd hold from gpiowr , gpmemwr 0.5 t clk t12 gpd setup time for gpiowr , gpmemwr for compressed or extended write mode 0.5 t clk t9 t1 t10 t2 t8 t11 t4 t3 t5 t6 t7 gpdrq gpdack gpaen gpd15Cgpd0 gpiowr , gpmemwr gptc t12 gpdbufoe
72 lan?sc520 microcontroller data sheet preliminary figure 38. gp-dma write cycle timing gp bus dma write cycle timing symbol parameter description advance information unit min max t clk gp-dma clock cycle 58 244 ns t1 gpdrq to gpdack assertion 2 t clk t2 gpdack asserted to gpaen and gpdbufoe assertion 1 t clk t3 gpiord , gpmemrd asserted to gpd valid 0.5 t clk t4 gpdack asserted to gpiord , gpmemrd assertion 2.5 t clk t5 gpiord , gpmemrd pulse width 1.5 t clk t6 gpdack asserted to gptc assertion 3.5 t clk t7 gptc pulse width 1.5 t clk t8 gpaen and gpdbufoe deasserted from command deasserted 1 t clk t9 gpdrq deasserted from gpdack assertion 0 ns t10 gpdack deasserted from command deasserted 1 t clk t11 gpiord , gpmemrd deasserted to gpd invalid 0 ns t9 t1 t10 t2 t8 t3 t11 t4 t5 t6 t7 gpdrq gpdack gpaen gpd15Cgpd0 gpiord , gpmemrd gptc gpdbufoe
lan?sc520 microcontroller data sheet 73 preliminary figure 39. ssi timing ssi timing symbol parameter description notes advance information unit min max t1 ssi_clk period 1 notes: 1. the clock period for the ssi interface is programmable as a divisor of the 33-mhz crystal input. rates provided are binary multiples from divide by 4 (~110 ns) to divide by 512 (~15526 ns). the actual period is affected by the frequency of the crysta l (33.000 mhz or 33.333 mhz). 110 ns t2 ssi_clk high time 55 ns t3 ssi_clk low time 55 ns t4 ssi_di setup time to sample edge 2 2. the sample/assert clock edge for the ssi interface is programmable. 3ns t5 ssi_di hold time from sample edge 2 3ns t6 ssi_do hold time from assert edge 2 0ns t7 ssi_do setup to sample edge 2,3 3. t clk refers to the programmed period for the ssi_clk pin. (0.5 t clk ) C 5 ns t8 ssi_do high impedance from sample edge of last bit 2,3 0.5 t clk (0.5 t clk ) + 5 ns t1 t2 t3 t7 t4 t5 t6 t6 t8 ssi_clk ssi_di ssi_do notes: asserted on rising edge, sampled on falling edge.
74 lan?sc520 microcontroller data sheet preliminary figure 40. jtag boundary scan timing jtag timing symbol parameter description advance information unit min max t1 jtag_trst active pulse width 20 ns t2 jtag_tck period 40 ns t3 jtag_tck high time 15 ns t4 jtag_tck low time 15 ns t5 jtag_tms, jtag_tdi setup time 5 ns t6 jtag_tms, jtag_tdi hold time 10 ns t7 jtag_tdo delay 10 ns t8 input pin setup time 15 ns t9 input pin hold time 15 ns t10 output pin delay 15 ns t1 t2 t3 t4 t5 t6 t5 t6 t7 t8 t9 t10 jtag_trst jtag_tck jtag_tms jtag_tdi jtag_tdo input pin output pin
lan?sc520 microcontroller data sheet a-1 preliminary appendix a pin tables this appendix contains pin tables for the lansc520 microcontroller. several different tables are included with the following characteristics: n multiplexed signal tradeoffstable 16 on page a-2. n programmable i/o pins ordered by pio pin number and multiplexed signal name, respectively, including a column showing pin configurations following system resettable 17 on page a-4 and table 18 on page a-5. n pin summary showing signal name and alternate function, pin number, i/o type, termination, reset state, output drive, and maximum loadtable 20 on page a-7. for pin tables showing pins sorted by pin number and signal name, respectively, see pin designations (pin number) on page 11 and pin designations (pin name) on page 13. for signal descriptions, see table 2, signal descrip- tions on page 17. in all tables the brackets, [ ], indicate alternate, multi- plexed functions, and braces, { }, indicate reset config- uration pins (pinstraps). the line over a pin name indicates an active low signal. the word pin refers to the physical wire; the word signal refers to the electrical signal that flows through it.
a-2 lan?sc520 microcontroller data sheet preliminary table 16. multiplexed signal trade-offs signal you want signal you give up pin # rom/flash control romcs1 gpcs1 b24 romcs2 gpcs2 c23 gp bus gpaen pio3 ae11 gpale pio0 ae12 gpbhe pio1 af12 gpcs0 pio27 ae4 gpcs1 romcs1 b24 gpcs2 romcs2 c23 gpcs3 pitgate2 ac21 gpcs4 tmrin1 aa24 gpcs5 tmrin0 ac20 gpcs6 tmrout1 ac23 gpcs7 tmrout0 ad23 gpdack0 pio12 ac8 gpdack1 pio11 ac9 gpdack2 pio10 ad9 gpdack3 pio9 ae9 gpdbufoe pio24 ad5 gpdrq0 pio8 af9 gpdrq1 pio7 af10 gpdrq2 pio6 ae10 gpdrq3 pio5 ad10 gpiocs16 pio25 ac4 gpirq0 pio23 ae5 gpirq1 pio22 af5 gpirq2 pio21 af6 gpirq3 pio20 ae6 gpirq4 pio19 ad6 gpirq5 pio18 ad7 gpirq6 pio17 ae7 gpirq7 pio16 af7 gpirq8 pio15 af8 gpirq9 pio14 ae8 gpirq10 pio13 ad8 gpmemcs16 pio26 ad4 gprdy pio2 af11 gptc pio4 ad11 serial ports cts2 pio28 af4 dcd2 pio30 ae3 dsr2 pio29 af3 rin2 pio31 ad3
lan?sc520 microcontroller data sheet a-3 preliminary clocks clktest clktimer a7 clktimer clktest a7 timers pitgate2 gpcs3 ac21 tmrin0 gpcs5 ac20 tmrin1 gpcs4 aa24 tmrout0 gpcs7 ad23 tmrout1 gpcs6 ac23 system test cf_dram wbmstr2 w24 cf_rom_gpcs wbmstr0 ad20 datastrb wbmstr1 ac24 wbmstr0 cf_rom_gpcs ad20 wbmstr1 datastrb ac24 wbmstr2 cf_dram w24 configuration pins (pinstraps) see configuration on page 26. programmable i/o pio0 gpale ae12 pio1 gpbhe af12 pio2 gprdy af11 pio3 gpaen ae11 pio4 gptc ad11 pio5 gpdrq3 ad10 pio6 gpdrq2 ae10 pio7 gpdrq1 af10 pio8 gpdrq0 af9 pio9 gpdack3 ae9 pio10 gpdack2 ad9 pio11 gpdack1 ac9 pio12 gpdack0 ac8 pio13 gpirq10 ad8 pio14 gpirq9 ae8 pio15 gpirq8 af8 pio16 gpirq7 af7 pio17 gpirq6 ae7 pio18 gpirq5 ad7 pio19 gpirq4 ad6 pio20 gpirq3 ae6 pio21 gpirq2 af6 pio22 gpirq1 af5 pio23 gpirq0 ae5 pio24 gpdbufoe ad5 pio25 gpiocs16 ac4 pio26 gpmemcs16 ad4 pio27 gpcs0 ae4 table 16. multiplexed signal trade-offs (continued) signal you want signal you give up pin #
a-4 lan?sc520 microcontroller data sheet preliminary table 17. pios sorted by pio number pio (default function) pin # multiplexed signal pin configuration following system reset pio0 ae12 gpale input with pullup pio1 af12 gpbhe input with pullup pio2 af11 gprdy input with pullup pio3 ae11 gpaen input with pullup pio4 ad11 gptc input with pullup pio5 ad10 gpdrq3 input with pulldown pio6 ae10 gpdrq2 input with pulldown pio7 af10 gpdrq1 input with pulldown pio8 af9 gpdrq0 input with pulldown pio9 ae9 gpdack3 input with pullup pio10 ad9 gpdack2 input with pullup pio11 ac9 gpdack1 input with pullup pio12 ac8 gpdack0 input with pullup pio13 ad8 gpirq10 input with pullup pio14 ae8 gpirq9 input with pullup pio15 af8 gpirq8 input with pullup pio16 af7 gpirq7 input with pullup pio17 ae7 gpirq6 input with pullup pio18 ad7 gpirq5 input with pullup pio19 ad6 gpirq4 input with pullup pio20 ae6 gpirq3 input with pullup pio21 af6 gpirq2 input with pullup pio22 af5 gpirq1 input with pullup pio23 ae5 gpirq0 input with pullup pio24 ad5 gpdbufoe input with pullup pio25 ac4 gpiocs16 input with pullup pio26 ad4 gpmemcs16 input with pullup pio27 ae4 gpcs0 input with pullup pio28 af4 cts2 input with pullup pio29 af3 dsr2 input with pullup pio30 ae3 dcd2 input with pullup pio31 ad3 rin2 input with pullup
lan?sc520 microcontroller data sheet a-5 preliminary table 18. pios sorted by signal name multiplexed signal pio (default function) pin configuration following system reset pin # cts2 pio28 input with pullup af4 dcd2 pio30 input with pullup ae3 dsr2 pio29 input with pullup af3 gpaen pio3 input with pullup ae11 gpale pio0 input with pullup ae12 gpbhe pio1 input with pullup af12 gpcs0 pio27 input with pullup ae4 gpdack0 pio12 input with pullup ac8 gpdack1 pio11 input with pullup ac9 gpdack2 pio10 input with pullup ad9 gpdack3 pio9 input with pullup ae9 gpdbufoe pio24 input with pullup ad5 gpdrq0 pio8 input with pulldown af9 gpdrq1 pio7 input with pulldown af10 gpdrq2 pio6 input with pulldown ae10 gpdrq3 pio5 input with pulldown ad10 gpiocs16 pio25 input with pullup ac4 gpirq0 pio23 input with pullup ae5 gpirq1 pio22 input with pullup af5 gpirq10 pio13 input with pullup ad8 gpirq2 pio21 input with pullup af6 gpirq3 pio20 input with pullup ae6 gpirq4 pio19 input with pullup ad6 gpirq5 pio18 input with pullup ad7 gpirq6 pio17 input with pullup ae7 gpirq7 pio16 input with pullup af7 gpirq8 pio15 input with pullup af8 gpirq9 pio14 input with pullup ae8 gpmemcs16 pio26 input with pullup ad4 gprdy pio2 input with pullup af11 gptc pio4 input with pullup ad11 rin2 pio31 input with pullup ad3
a-6 lan?sc520 microcontroller data sheet preliminary pin list summary table column definitions the following paragraphs describe the individual columns of information in table 20, pin list summary, on page a-7. the pins are grouped alphabetically by function. column #1signal name, [alternate function], {pinstrap} this column denotes the primary and alternate func- tions of the pins. brackets, [ ], are used to indicate the alternate, multi- plexed function of a pin. braces, { }, are used to indicate the functionality of a pin only during a processor reset. these signals are called pinstraps. for pinstraps, see configuration on page 26. column #2pin # the pin number column identifies the pin number of the individual i/o signal on the package. column #3type definitions of the abbreviations in the type column are shown in table 19. column #4termination the termination column specifies the presence of pullups or pulldowns on the pins. column #5reset state definitions of the abbreviations in the reset state col- umn are shown in table 19. column #6output drive the output drive column shows the output amperage. column #7max load (pf) the max load column designates the capacitive load at which the i/o timing for that pin is guaranteed. column #8note the note column shows footnote numbers. table 19. pin list summary table abbreviations type definition none or not applicable. [ ] brackets signify a programmable alternate state. { } reset configuration pin. these are the configuration pins latched during reset. active used in the reset state column to indicate signals active during reset. analog pin is an analog input. b bidirectional. h driven high (a logical 1). i pin is an input. iod input or open-drain output. l driven low (a logical 0). latched used in the reset state column to indicate a signal latched on reset. na not applicable. o pin is an active output. od open-drain output. osc oscillator. pd built-in pulldown resistor (~100C150 k w). power power pins. pu built-in pullup resistor (~100C150 k w). sti pin is a schmitt trigger input. sts sustained three-state (pci drive). ts three-state output.
lan?sc520 microcontroller data sheet a-7 preliminary table 20. pin list summary signal name [alternate function] {pinstrap} pin # type termination reset state output drive max load (pf) sdram ba0 t25 o h 12/18/24 ma 50 pf ba1 u25 o h 12/18/24 ma 50 pf clkmemin a4 i i clkmemout b19 o active 24 ma 50 pf ma0 l25 o h 12/18/24 ma 50 pf ma1 l26 o h 12/18/24 ma 50 pf ma2 m26 o h 12/18/24 ma 50 pf ma3 m25 o h 12/18/24 ma 50 pf ma4 n25 o h 12/18/24 ma 50 pf ma5 n26 o h 12/18/24 ma 50 pf ma6 p26 o h 12/18/24 ma 50 pf ma7 p25 o h 12/18/24 ma 50 pf ma8 r25 o h 12/18/24 ma 50 pf ma9 r26 o h 12/18/24 ma 50 pf ma10 t26 o h 12/18/24 ma 50 pf ma11 u26 o h 12/18/24 ma 50 pf ma12 v26 o h 12/18/24 ma 50 pf md0 b7 b i 12/18/24 ma 50 pf md1 a8 b i 12/18/24 ma 50 pf md2 b9 b i 12/18/24 ma 50 pf md3 a10 b i 12/18/24 ma 50 pf md4 b11 b i 12/18/24 ma 50 pf md5 a12 b i 12/18/24 ma 50 pf md6 b13 b i 12/18/24 ma 50 pf md7 a14 b i 12/18/24 ma 50 pf md8 b15 b i 12/18/24 ma 50 pf md9 a16 b i 12/18/24 ma 50 pf md10 b17 b i 12/18/24 ma 50 pf md11 a18 b i 12/18/24 ma 50 pf md12 b20 b i 12/18/24 ma 50 pf md13 a21 b i 12/18/24 ma 50 pf md14 a22 b i 12/18/24 ma 50 pf md15 b23 b i 12/18/24 ma 50 pf md16 b8 b i 12/18/24 ma 50 pf md17 a9 b i 12/18/24 ma 50 pf md18 b10 b i 12/18/24 ma 50 pf md19 a11 b i 12/18/24 ma 50 pf md20 b12 b i 12/18/24 ma 50 pf md21 a13 b i 12/18/24 ma 50 pf md22 b14 b i 12/18/24 ma 50 pf md23 a15 b i 12/18/24 ma 50 pf
a-8 lan?sc520 microcontroller data sheet preliminary md24 b16 b i 12/18/24 ma 50 pf md25 a17 b i 12/18/24 ma 50 pf md26 b18 b i 12/18/24 ma 50 pf md27 a19 b i 12/18/24 ma 50 pf md28 a20 b i 12/18/24 ma 50 pf md29 b21 b i 12/18/24 ma 50 pf md30 a23 b i 12/18/24 ma 50 pf md31 a24 b i 12/18/24 ma 50 pf mecc0 c25 b i 12/18/24 ma 50 pf mecc1 d26 b i 12/18/24 ma 50 pf mecc2 w26 b i 12/18/24 ma 50 pf mecc3 y25 b i 12/18/24 ma 50 pf mecc4 c26 b i 12/18/24 ma 50 pf mecc5 d25 b i 12/18/24 ma 50 pf mecc6 y26 b i 12/18/24 ma 50 pf scasa f25 o h 12/18/24 ma 50 pf scasb f26 o h 12/18/24 ma 50 pf scs0 v25 o h 12/18 ma 50 pf scs1 w25 o h 12/18 ma 50 pf scs2 j25 o h 12/18 ma 50 pf scs3 j26 o h 12/18 ma 50 pf sdqm0 g25 o h 12/18/24 ma 50 pf sdqm1 h26 o h 12/18/24 ma 50 pf sdqm2 g26 o h 12/18/24 ma 50 pf sdqm3 h25 o h 12/18/24 ma 50 pf srasa k25 o h 12/18/24 ma 50 pf srasb k26 o h 12/18/24 ma 50 pf swea e26 o h 12/18/24 ma 50 pf sweb e25 o h 12/18/24 ma 50 pf rom/flash control bootcs ab25 o h 12 ma 70 pf flashwr ab24 o h 24 ma 70 pf rombufoe aa25 o h 12 ma 70 pf romcs1 [gpcs1 ] b24 o [o] h 12 ma 70 pf romcs2 [gpcs2] c23 o [o] h 12 ma 70 pf romrd ab23 o h 24 ma 70 pf pci bus ad0 ac2 sts-b l ad1 ac1 sts-b l ad2 ab1 sts-b l ad3 ab2 sts-b l table 20. pin list summary (continued) signal name [alternate function] {pinstrap} pin # type termination reset state output drive max load (pf)
lan?sc520 microcontroller data sheet a-9 preliminary ad4 aa2 sts-b l ad5 aa1 sts-b l ad6 y1 sts-b l ad7 y2 sts-b l ad8 w1 sts-b l ad9 v1 sts-b l ad10 v2 sts-b l ad11 u2 sts-b l ad12 u1 sts-b l ad13 t1 sts-b l ad14 t2 sts-b l ad15 r2 sts-b l ad16 k2 sts-b l ad17 j2 sts-b l ad18 j1 sts-b l ad19 h1 sts-b l ad20 h2 sts-b l ad21 g2 sts-b l ad22 g1 sts-b l ad23 f1 sts-b l ad24 e2 sts-b l ad25 e1 sts-b l ad26 d1 sts-b l ad27 d2 sts-b l ad28 b2 sts-b l ad29 b1 sts-b l ad30 a1 sts-b l ad31 a2 sts-b l cbe0 w2 sts-b l cbe1 r1 sts-b l cbe2 k1 sts-b l cbe3 f2 sts-b l clkpciin g3 i i clkpciout a6 o active devsel m1 sts-b ts frame l1 sts-b ts gnt0 m3 o ts gnt1 n4 o ts gnt2 p3 o ts gnt3 t3 o ts gnt4 u4 o ts inta k3 i i table 20. pin list summary (continued) signal name [alternate function] {pinstrap} pin # type termination reset state output drive max load (pf)
a-10 lan?sc520 microcontroller data sheet preliminary intb j3 i i intc h3 i i intd h4 i i irdy l2 sts-b ts par p1 sts-b l perr n2 sts-b ts req0 l3 i i req1 n3 i i req2 p4 i i req3 r3 i i req4 u3 i i rst a5 o l serr p2 sts-i ts stop n1 sts-b ts trdy m2 sts-b ts gp bus gpa0 j24 o h 12 ma 70 pf gpa1 g4 o h 12 ma 70 pf gpa2 k24 o h 12 ma 70 pf gpa3 j23 o h 12 ma 70 pf gpa4 l24 o h 12 ma 70 pf gpa5 h24 o h 12 ma 70 pf gpa6 c1 o h 12 ma 70 pf gpa7 f23 o h 12 ma 70 pf gpa8 m24 o h 12 ma 70 pf gpa9 c2 o h 12 ma 70 pf gpa10 m23 o h 12 ma 70 pf gpa11 n23 o h 12 ma 70 pf gpa12 n24 o h 12 ma 70 pf gpa13 p24 o h 12 ma 70 pf gpa14 r24 o h 12 ma 70 pf gpa15 {rstld0} c24 o {i} pd latched 12 ma 70 pf gpa16 {rstld1} d24 o {i} pd latched 12 ma 70 pf gpa17 {rstld2} e24 o {i} pd latched 12 ma 70 pf gpa18 {rstld3} b22 o {i} pd latched 12 ma 70 pf gpa19 {rstld4} c21 o {i} pd latched 12 ma 70 pf gpa20 {rstld5} c14 o {i} pd latched 12 ma 70 pf table 20. pin list summary (continued) signal name [alternate function] {pinstrap} pin # type termination reset state output drive max load (pf)
lan?sc520 microcontroller data sheet a-11 preliminary gpa21 {rstld6} c19 o {i} pd latched 12 ma 70 pf gpa22 {rstld7} f3 o {i} pd latched 12 ma 70 pf gpa23 {amdebug_dis} d3 o {i} pd latched 12 ma 70 pf gpa24 {inst_trce} d4 o {i} pd latched 12 ma 70 pf gpa25 {debug_enter} c3 o {i} pd latched 12 ma 70 pf gpd0 c4 b pu i 12 ma 70 pf gpd1 b5 b pu i 12 ma 70 pf gpd2 c7 b pu i 12 ma 70 pf gpd3 c8 b pu i 12 ma 70 pf gpd4 c9 b pu i 12 ma 70 pf gpd5 d9 b pu i 12 ma 70 pf gpd6 d10 b pu i 12 ma 70 pf gpd7 c10 b pu i 12 ma 70 pf gpd8 c11 b pu i 12 ma 70 pf gpd9 c12 b pu i 12 ma 70 pf gpd10 c13 b pu i 12 ma 70 pf gpd11 d13 b pu i 12 ma 70 pf gpd12 d14 b pu i 12 ma 70 pf gpd13 c15 b pu i 12 ma 70 pf gpd14 c17 b pu i 12 ma 70 pf gpd15 d17 b pu i 12 ma 70 pf gpiord g24 o h 12 ma 70 pf gpiowr c16 o h 12 ma 70 pf gpmemrd f24 o h 12 ma 70 pf gpmemwr c18 o h 12 ma 70 pf gpreset ac22 o h 6 ma 70 pf pio0 [gpale] ae12 b [o] pu i 6 ma 30 pf pio1 [gpbhe ] af12 b [o] pu i 6 ma 30 pf pio2 [gprdy] af11 b [sti] pu i 6 ma 30 pf pio3 [gpaen] ae11 b [o] pu i 6 ma 30 pf pio4 [gptc] ad11 b [o] pu i 6 ma 30 pf pio5 [gpdrq3] ad10 b [i] pd i 6 ma 30 pf pio6 [gpdrq2] ae10 b [i] pd i 6 ma 30 pf table 20. pin list summary (continued) signal name [alternate function] {pinstrap} pin # type termination reset state output drive max load (pf)
a-12 lan?sc520 microcontroller data sheet preliminary pio7 [gpdrq1] af10 b [i] pd i 6 ma 30 pf pio8 [gpdrq0] af9 b [i] pd i 6 ma 30 pf pio9 [gpdack3 ] ae9 b [o] pu i 6 ma 30 pf pio10 [gpdack2 ] ad9 b [o] pu i 6 ma 30 pf pio11 [gpdack1] ac9 b [o] pu i 6 ma 30 pf pio12 [gpdack0] ac8 b [o] pu i 6 ma 30 pf pio13 [gpirq10] ad8 b [i] pu i 6 ma 30 pf pio14 [gpirq9] ae8 b [i] pu i 6 ma 30 pf pio15 [gpirq8] af8 b [i] pu i 6 ma 30 pf pio16 [gpirq7] af7 b [i] pu i 6 ma 30 pf pio17 [gpirq6] ae7 b [i] pu i 6 ma 30 pf pio18 [gpirq5] ad7 b [i] pu i 6 ma 30 pf pio19 [gpirq4] ad6 b [i] pu i 6 ma 30 pf pio20 [gpirq3] ae6 b [i] pu i 6 ma 30 pf pio21 [gpirq2] af6 b [i] pu i 6 ma 30 pf pio22 [gpirq1] af5 b [i] pu i 6 ma 30 pf pio23 [gpirq0] ae5 b [i] pu i 6 ma 30 pf pio24 [gpdbufoe ] ad5 b [o] pu i 6 ma 30 pf pio25 [gpiocs16 ] ac4 b [sti] pu i 6 ma 30 pf pio26 [gpmemcs16 ] ad4 b [sti] pu i 6 ma 30 pf pio27 [gpcs0 ] ae4 b [o] pu i 6 ma 30 pf serial ports cts1 v3 i pu i dcd1 v4 i pu i dsr1 y3 i pu i dtr1 w3 o h 6 ma 30 pf dtr2 ae23 o h 6 ma 30 pf table 20. pin list summary (continued) signal name [alternate function] {pinstrap} pin # type termination reset state output drive max load (pf)
lan?sc520 microcontroller data sheet a-13 preliminary pio28 [cts2 ] af4 b [i] pu i 6 ma 30 pf pio29 [dsr2 ] af3 b [i] pu i 6 ma 30 pf pio30 [dcd2 ] ae3 b [i] pu i 6 ma 30 pf pio31 [rin2 ] ad3 b [i] pu i 6 ma 30 pf rin1 aa3 i pu i rts1 w4 o h 6 ma 30 pf rts2 ad22 o h 6 ma 30 pf sin1 ae2 i pu i sin2 v24 i pu i sout1 af2 o h 6 ma 30 pf sout2 u23 o h 6 ma 30 pf ssi_clk ad19 o h 6 ma 30 pf ssi_di ae19 sti pu i ssi_do af19 od l 6 ma 30 pf clocks and reset 32kxtal1 af26 osc active 32kxtal2 ae26 osc active 33mxtal1 ab26 osc active 33mxtal2 ac26 osc active clktimer [clktest] a7 i [o] pu i 18 ma 50 pf lf_pll1 af24 osc active prgreset d20 sti i pwrgood c20 sti i jtag jtag_tck ad21 i pu i jtag_tdi af21 i pu i jtag_tdo af22 o/ts pu ts 6 ma 30 pf jtag_tms ae21 i pu i jtag_trst ae22 i pd i amdebug interface br/tc ad24 i pd i cmdack u24 o l 6 ma 30 pf stop/tx af17 o l 6 ma 30 pf trig/trace ac13 o l 6 ma 30 pf system test cf_dram [wbmstr2] {cfg2} w24 o [o] {i} pd latched 6 ma 30 pf table 20. pin list summary (continued) signal name [alternate function] {pinstrap} pin # type termination reset state output drive max load (pf)
a-14 lan?sc520 microcontroller data sheet preliminary cf_rom_gpcs [wbmstr0] {cfg0} ad20 o [o] {i} pd latched 6 ma 30 pf datastrb [wbmstr1] {cfg1} ac24 o [o] {i} pd latched 6 ma 30 pf timers pitgate2 [gpcs3 ] ac21 i [o] pu i 6 ma 30 pf pitout2 {cfg3} y24 o {i} pd latched 6 ma 30 pf tmrin0 [gpcs5 ] ac20 i [o] pu i 6 ma 30 pf tmrin1 [gpcs4 ] aa24 i [o] pu i 6 ma 30 pf tmrout0 [gpcs7 ] ad23 o [o] h 6 ma 30 pf tmrout1 [gpcs6 ] ac23 o [o] h 6 ma 30 pf power and ground bbatsen b25 analog latched gnd l11 power gnd l12 power gnd l13 power gnd l14 power gnd l15 power gnd l16 power gnd m11 power gnd m12 power gnd m13 power gnd m14 power gnd m15 power gnd m16 power gnd n11 power gnd n12 power gnd n13 power gnd n14 power gnd n15 power gnd n16 power gnd p11 power gnd p12 power gnd p13 power gnd p14 power gnd p15 power gnd p16 power table 20. pin list summary (continued) signal name [alternate function] {pinstrap} pin # type termination reset state output drive max load (pf)
lan?sc520 microcontroller data sheet a-15 preliminary gnd r11 power gnd r12 power gnd r13 power gnd r14 power gnd r15 power gnd r16 power gnd t11 power gnd t12 power gnd t13 power gnd t14 power gnd t15 power gnd t16 power gnd_anlg a25 power vcc_anlg b26 power vcc_core ac14 power vcc_core ac15 power vcc_core ac5 power vcc_core ac6 power vcc_core ac7 power vcc_core d11 power vcc_core d12 power vcc_core d18 power vcc_core d19 power vcc_core e4 power vcc_core f4 power vcc_core g23 power vcc_core h23 power vcc_core p23 power vcc_core r23 power vcc_core r4 power vcc_core t4 power vcc_i/o aa23 power vcc_i/o aa4 power vcc_i/o ac10 power vcc_i/o ac11 power vcc_i/o ac18 power vcc_i/o ac19 power vcc_i/o d15 power vcc_i/o d16 power vcc_i/o d21 power vcc_i/o d22 power vcc_i/o d5 power table 20. pin list summary (continued) signal name [alternate function] {pinstrap} pin # type termination reset state output drive max load (pf)
a-16 lan?sc520 microcontroller data sheet preliminary vcc_i/o d6 power vcc_i/o d7 power vcc_i/o d8 power vcc_i/o j4 power vcc_i/o k23 power vcc_i/o k4 power vcc_i/o l23 power vcc_i/o l4 power vcc_i/o m4 power vcc_i/o v23 power vcc_i/o w23 power vcc_i/o y23 power vcc_i/o y4 power vcc_rtc a26 power no connects 1 nc a3 nc aa26 nc ab3 nc ab4 nc ac12 nc ac16 nc ac17 nc ac25 nc ac3 nc ad1 nc ad12 nc ad13 nc ad14 nc ad15 nc ad16 nc ad17 nc ad18 nc ad2 nc ad25 nc ad26 nc ae1 nc ae13 nc ae14 nc ae15 nc ae16 nc ae17 nc ae18 table 20. pin list summary (continued) signal name [alternate function] {pinstrap} pin # type termination reset state output drive max load (pf)
lan?sc520 microcontroller data sheet a-17 preliminary nc ae20 nc ae24 nc ae25 nc af1 nc af13 nc af14 nc af15 nc af16 nc af18 nc af20 nc af23 nc af25 nc b3 nc b4 nc b6 nc c22 nc c5 nc c6 nc d23 nc e23 nc e3 nc t23 nc t24 notes: 1. the ncs are true "no connects" and should be left disconnected. table 20. pin list summary (continued) signal name [alternate function] {pinstrap} pin # type termination reset state output drive max load (pf)
a-18 lan?sc520 microcontroller data sheet preliminary
lan?sc520 microcontroller data sheet b-1 preliminary appendix b physical dimensions 388-pin plastic bga (pbga) package top view a1 corner a1 corner i.d. seating plane 35.00 bsc 2.20 2.46 0.50 0.70 0.51 0.61 encapsulation 17.0 x 14.0 min flat area 4x .20 4.00 x 45 4x top side (die side) side view a 30 typ detail a scale:none 3x 0.50 r. 0.15 c 0.15 c 0.15 c b 35.00 bsc 29.90 30.10 28.00 bsc c a
b-2 lan?sc520 microcontroller data sheet preliminary bottom view bottom view all rows and columns 0.635 bsc 1.27 bsc 31.75 bsc a1 corner a1 corner i.d. 16-038-bga388-2 et118 10.26.98 lv 0.60 0.90 .30 .10 cab c 388x (datum b) 0.635 bsc 31.75 bsc (datum a)
lan?sc520 microcontroller data sheet b-3 preliminary circuit board layout considerations there are two basic ways to set up a bga ball pad, sol- der-mask defined and solder-pad defined. n solder-mask defined is when the solder mask opening is smaller than the copper pad, so the solder surface is defined by the solder mask rather than the copper pad. n solder-pad defined is when the copper pad is smaller than the solder mask, so the solder surface is defined by the copper pad. a problem can occur when you mix these two methods. for example, if the chip is solder-pad defined and the board is pad-defined, then a problem can occur where there is more surface area on the board making contact than on the part itself. when the part heats and cools, a different amount of stress is placed on the chip than on the board (because there is more surface area sol- dered on the board), and the chip can warp. the pad definition on the board should match the chip. the lansc520 microcontroller is solder-mask de- fined, so the circuit board design should be solder- mask defined with a solder-mask opening of 0.60 mm over a 0.80-mm pad as shown in figure 41. figure 41. bga ball pad layout copper pad 0.80 mm solder 0.60 mm mask opening exposed copper solder mask covered copper top view of bga pad printed circuit board copper pad solder mask side view of bga pad
b-4 lan?sc520 microcontroller data sheet preliminary
lan?sc520 microcontroller data sheet c-1 preliminary table 21. related amd productse86? family devices device 1 notes: 1. 186 = 16-bit microcontroller and 80c186-compatible (except where noted otherwise); 188 = 16-bit microcontroller with 8-bit external data bus and 80c188-compatible (except where noted otherwise); lv = low voltage description 80c186/80c188 16-bit microcontroller 80l186/80l188 low-voltage, 16-bit microcontroller am186?em/am188?em high-performance, 16-bit embedded microcontroller am186emlv/am188emlv high-performance, 16-bit embedded microcontroller am186es/am188es high-performance, 16-bit embedded microcontroller am186eslv/am188eslv high-performance, 16-bit embedded microcontroller am186ed high-performance, 80c186- and 80c188-compatible, 16-bit embedded microcontroller with 8- or 16-bit external data bus am186edlv high-performance, 80c186- and 80c188-compatible, low-voltage, 16-bit embedded microcontroller with 8- or 16-bit external data bus am186er/am188er high-performance, low-voltage, 16-bit embedded microcontroller with 32 kbyte of internal ram am186cc high-performance, 16-bit embedded communications controller am186ch high-performance, 16-bit embedded hdlc microcontroller am186cu high-performance, 16-bit embedded usb microcontroller lansc300 high-performance, highly integrated, low-voltage, 32-bit embedded microcontroller lansc310 high-performance, single-chip, 32-bit embedded pc/at-compatible microcontroller lansc400 high-performance, single-chip, low-power, pc/at-compatible microcontroller lansc410 high-performance, single-chip, pc/at-compatible microcontroller lansc520 high-performance, single-chip, 32-bit embedded microcontroller am386?dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus am386?sx high-performance, 32-bit embedded microprocessor with 16-bit external data bus am486?dx high-performance, 32-bit embedded microprocessor with 32-bit external data bus am x 586? high-performance, 32-bit embedded microprocessor with 32-bit external data bus amd-k6?e high-performance, 32-bit embedded microprocessor with 64-bit external data bus amd-k6?-2e high-performance, 32-bit embedded microprocessor with 64-bit external data bus and 3dnow!? technology am386 ? sx/dx microprocessors am486 ? dx microprocessor e86 ? famil y of embedded micro p rocessors and microcontrollers am186es and am188?em am188emlv microcontrollers am188er microprocessors 16- and 32-bit microcontrollers 16-bit microcontrollers amd-k6?e microprocessor amd-k6?-2e microprocessor am5 x 86 microprocessor am186cc communications controller am186?cu usb microcontroller am186ch hdlc microcontroller 80c186 and 80c188 microcontrollers am188es microcontrollers am186em and microcontrollers 80l186 and 80l188 microcontrollers am186emlv & microcontrollers am186eslv & am188eslv am186er and microcontrollers am186ed am186edlv microcontroller microcontroller appendix c customer support lan?sc310 microcontroller lansc300 microcontroller lansc410 microcontroller lansc400 microcontroller lansc520 microcontroller
c-2 lan?sc520 microcontroller data sheet preliminary related documents the following documents contain additional information that will be useful in designing an embedded applica- tion based on the lansc520 microcontroller. n lan?sc520 microcontroller register set manual , order #22005, fully describes all the registers re- quired to program the microcontroller. n lan?sc520 microcontroller users manual , order #22004, provides a functional description of the mi- crocontroller for both hardware and software de- signers. n the am486? microprocessor software users man- ual, order #18497, includes the complete instruction set for the integrated am5 x 86 cpu. other information of interest: n am5 x 86 ? microprocessor family data sheet , order #19751 n am486 ? dx/dx2 microprocessor hardware refer- ence manual , order #17965 n e86 family products and development tools cd , order #21058, provides a single-source multimedia tool for customer evaluation of amd products, as well as fusione86 partner tools and technologies that support the e86? family. technical documen- tation is included on the cd in pdf format. to order literature, contact the nearest amd sales of- fice or call the literature center at one of the numbers listed on the back cover of this manual. in addition, all these documents are available in pdf form on the amd web site. to access the amd home page, go to www.amd.com. then follow the embedded processor link for information about e86 microcontrollers. additional information the following non-amd documents and sources pro- vide additional information that may be of interest to lansc520 microcontroller users: n pci local bus specification , december 18, 1998, pci special interest group, 800-433-5177 (us), 503-693-6232 (international), www.pcisig.com. n ieee std 1149.1-1990 standard test access port and boundary-scan architecture, (order #sh16626-nyf), institute of electrical and elec- tronic engineers, inc., 800-678-4333, www.ieee.org. n pci system architecture , mindshare, inc., reading, ma: addison-wesley, 1995, isbn 0-201-40993-3. n isa system architecture , mindshare, inc., reading, ma: addison-wesley, 1995, isbn 0-201-40996-8. n 80486 system architecture, mindshare, inc., read- ing, ma: addison-wesley, 1995, isbn 0-201- 40994-1 n the indispensable pc hardware book , hans-peter messmer, wokingham, england: addison-wesley, 1995, isbn 0-201-87697-3. customer development platform the lansc520 microcontroller customer develop- ment platform (cdp) is provided as a test and develop- ment platform to illustrate the capabilities of the lansc520 microcontroller using the pci bus and an on-board 10/100 mbit/s ethernet connection. in addi- tion, the cdp serves as a platform for embedded prod- uct development using the lansc520 microcontroller, am79c972 ethernet controller, and the pci bus. the lansc520 microcontroller cdp enables develop- ers to benchmark their embedded, network-ready ap- plications, understand the functionality of the microcontroller, and to know how to wire an lansc520 microcontroller system using off-the-shelf components. the cdp board also demonstrates how the embedded pci bus controller works well with other pci-ready pe- ripherals. third-party development support products the fusione86 program of partnerships for applica- tion solutions provides the customer with an array of products designed to meet critical time-to-market needs. products and solutions available from the amd fusione86 partners include protocol stacks, emulators, hardware and software debuggers, board-level prod- ucts, and software development tools, among others. in addition, mature development tools and applications for the x86 platform are widely available in the general marketplace.
lan?sc520 microcontroller data sheet c-3 preliminary customer service the amd customer service network includes u.s. of- fices, international offices, and a customer training cen- ter. expert technical assistance is available from the amd worldwide staff of field application engineers and factory support staff to answer e86 and comm86 fam- ily hardware and software development questions. hotline and world wide web support for answers to technical questions, amd provides e-mail support as well as a toll-free number for direct access to our corporate applications hotline. the amd world wide web home page provides the lat- est product information, including technical information and data on upcoming product releases. in addition, epd codekit software on the web site provides tested source code example applications. additional contact information is listed on the back of this datasheet. for technical support questions on all e86 and comm86 products, send e-mail to epd.support@amd.com . world wide web home page to access the amd home page go to: www.amd.com . then follow the embedded processors link for infor- mation about e86 family and comm86? products. questions, requests, and input concerning amds www pages can be sent via e-mail to web.feedback@amd.com . documentation and literature free information such as data books, users manuals, data sheets, application notes, the e86? family prod- ucts and development tools cd , order #21058, and other literature is available with a simple phone call. in- ternationally, contact your local amd sales office for product literature, or go to www.amd.com/support/lit- erature.html . additional contact information is listed on the back of this data sheet. corporate applications hotline (800) 222-9323 toll-free for u.s. and canada 44-(0) 1276-803-299 u.k. and europe hotline literature ordering (800) 222-9323 toll-free for u.s. and canada
c-4 lan?sc520 microcontroller data sheet preliminary
lan?sc520 microcontroller data sheet index-1 preliminary index a a20 gate, 32 address mapping, 31 amdebug technology description, 30 parallel, 30 pin summary, a-13 serial, 30 signal descriptions, 23 applications description, 33 digital set top box, 36 smart residential gateway, 34 thin client, 35 architecture overview, 28 x86 instruction set, 30 b block diagram, 29 bootstraps see configuration. c capacitance crystal, 51 derating curves, 51 non-pci interface, 51 pci interface, 51 chip select gp bus signal description, 24 circuit board layout, b-3 clock 32.768-khz crystal selection, 41 33.333-mhz crystal speed, 43 33-mhz crystal selection, 42 backup battery, 46 circuit diagrams, 46 block diagram of clock source, 39 bypassing internal oscillators, 44 circuit with backup battery, 47 circuit without backup battery, 47 control, 38 crystal selection, 41 crystal speeds, 38 generation and control, 38 internal, 39 multiplexed signal trade-offs, a-3 not using backup battery, 46 overview, 31 pin loading, 40 pin summary, a-13 real-time clock (rtc) voltage monitor, 45 rtc voltage monitor block diagram, 45 rtc voltage monitor specifications, 46 sdram clock timing, 68 signal descriptions, 22 specifications, 40 system clock block diagram, 38 configuration multiplexed signal trade-offs, a-3 signal descriptions, 26 cpu x86 instruction set, 30 crystal 32.768-khz crystal circuit, 41 32.768-khz crystal selection, 41 33.333-mhz crystal speed, 43 33-mhz crystal selection, 42 3rd overtone crystal circuit implementation, 42 capacitance, 51 crystal speeds, 38 selecting, 41 customer support customer development platform, c-2 documentation and literature, c-3 hotline and web, c-3 literature ordering, c-3 ordering the microcontroller, 2 related amd products/devices, c-1 related documents/information, c-2 third-party development support products, c-2 web home page, c-3 d dc characteristics, 50 operating ranges, 48 voltage for non-pci interface pins, 49, 51 debugging see also amdebug technology. features and system test, 32
preliminary index-2 lan?sc520 microcontroller data sheet jtag boundary scan test interface, 32 jtag signal descriptions, 23 derating curves, 51 dma gp bus dma read cycle, 71 gp bus dma write cycle, 72 integrated controller, 31 documentation see customer support. dram see sdram. e lan?sc520 microcontroller application examples, 33 architectural overview, 28 block diagram, 29 capacitance, 51 circuit board layout, b-3 dc characteristics, 50 distinctive characteristics, 1 documentation, c-2 general description, 1 logic diagram by default pin function, 7 logic diagram by interface, 6 maximum ratings, 48 operating ranges, 48 ordering information, 2 pbga package, b-1 peripherals (overview), 31 physical dimensions, b-1 pin connection diagram, 8 pin designations, 10 pin tables (appendix a), a-1 power characteristics, 56 programmable address region (par) registers, 31 related amd e86 family devices, c-1 switching characteristics and waveforms, 58 thermal characteristics, 56 voltage levels, 48C49 f flash addressing mapping, 31 controller description, 30 multiplexed signal trade-offs, a-2 pin summary, a-8 signal descriptions, 18 write cycles, 65 g gp bus chip-select signal descriptions, 24 description, 31 dma read cycle, 71 dma write cycle, 72 multiplexed signal trade-offs, a-2 pin summary, a-10 signal descriptions, 19 timing, 69 ground pin summary, a-14 h hotline and world wide web support, c-3 i i/o programmable i/o (pio) signal descriptions, 25 interrupts programmable interrupt controller (pic), 31 j jtag boundary scan test interface, 32 pin summary, a-13 signal descriptions, 23 timing, 74 l literature see customer support. logic diagram by default pin function, 7 by interface, 6 m maximum ratings, 48 multiplexed functions signal trade-offs, a-2 n no connect (nc) pin summary, a-16
preliminary lan?sc520 microcontroller data sheet index-3 o operating ranges, 48 ordering information, 2 p package pbga physical dimensions, b-1 pa r programmable address region registers, 31 pbga package physical dimensions, b-1 thermal characteristics, 56 pci bus ac timing, 58 capacitance, 51 description, 30 pin summary, a-8 signal descriptions, 18 switching test waveforms, 58 timing, 65 voltage, 49 peripherals integrated, description of, 31 physical dimensions, b-1 pic (programmable interrupt controller), 31 pins see also signals. clock pin loading, 40 pin and signal tables, 10 pin connection diagram, 8 pin designations, 10 pin designations by pin name, 13 pin designations sorted by pin number, 11 pin tables (appendix a), a-1 multiplexed signal trade-offs table, a-2 pin list summary table, a-7 pios sorted by pio number table, a-4 pios sorted by signal name table, a-5 pio see programmable i/o (pio). power characteristics, 56 pin summary, a-14 power dissipation, 56 signal descriptions, 27 supply current, 56 voltage levels, 48 power-on reset timing, 59 programmable i/o (pio) multiplexed signal trade-offs, a-3 signal descriptions, 25 sorted by pin number, a-4 sorted by signal name, a-5 r real-time clock (rtc) backup battery, 46 circuit with backup battery, 47 circuit without backup battery, 47 not using backup battery, 46 voltage monitor, 45 voltage monitor block diagram, 45 voltage monitor specifications, 46 reset pin summary, a-13 power-on reset timing, 59 signal descriptions, 22 soft cpu reset, 32 timing with power applied, 61 rom address mapping, 31 controller description, 30 multiplexed signal trade-offs, a-2 pin summary, a-8 signal descriptions, 18 timing, 63 rtc see real-time clock (rtc). s sdram address mapping, 31 clock timing, 68 controller description, 30 error correction code (ecc), 30 pin summary, a-7 signal descriptions, 17 timing, 66 serial ports multiplexed signal trade-offs, a-2 pin summary, a-12 signal descriptions, 21 signals see also pins. multiplexed signal trade-offs table, a-2 signal description table, 17 signal descriptions, 16 software timer, 32 ssi see synchronous serial interface (ssi). switching characteristics and waveforms gp bus, 69 jtag, 74 non-pci bus interface pins, 58
preliminary index-4 lan?sc520 microcontroller data sheet over commercial/industrial operating ranges, 59 pci bus, 65 pci bus interface pins, 58 power-on reset, 59 reset with power applied, 61 rom, 63 sdram, 66 ssi, 73 synchronous serial interface (ssi) description, 32 timing, 73 system test multiplexed signal trade-offs, a-3 pin summary, a-13 signal descriptions, 23 t technical support see customer support. testing jtag boundary scan test interface, 32 system test and debug features, 32 system test multiplexed signal trade-offs, a-3 system test pin summary, a-13 system test signal descriptions, 23 thermal characteristics, 56 equations, 57 timers description, 32 multiplexed signal trade-offs, a-3 pin summary, a-14 signal descriptions, 25 timing see switching characteristics and waveforms. u uarts description, 32 v voltage for non-pci interface pins, 49 for pci interface pins, 49 maximum ratings, 48 operating ranges, 48 w watchdog timer, 32 www home page, c-3 support, c-3
lan?sc520 microcontroller data sheet preliminary trademarks amd, the amd logo, and combinations thereof, amd athlon, lan, amdebug, pcnet, e86, am186, am188 and comm86 are trademarks; am5 x 86, am386, am486 and amd-k6 are registered trademarks and fusione86 is a servicemark of advanced micro devices, inc. microsoft and windows are registered trademarks of microsoft corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies. disclaimer the contents of this document are provided in connection with advanced micro devices, inc. ("amd") products. amd makes no repr esentations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make c hanges to speci- fications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or oth erwise, to any intel- lectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, am d assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, th e implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical impla nt into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's p roduct could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discont inue or make changes to its products at any time without notice. ?2001 advanced micro devices, inc. all rights reserved.
amendment ? copyright 2001 advanced micro devices, inc. all rights reserved. publication# 22003 rev: b amendment/ 1 issue date: may 2001 lansc520 microcontroller datasheet this document amends the lansc520 microcontroller datasheet , order #22003b. documentation defects and corrections the following corrections apply: on page 2 of the datasheet, add a new temperature range: i = industrial (t a = ?40 c to +85 c) where: t a = ambient temperature also on page 2, add a new row to the valid combi- nations table. the complete revised table is repro- duced here: on page 48, in the heading ?operating ranges at commercial temperatures,? change ?commercial? to ?commercial and industrial.? also on page 48, add a new operating range param- eter, t ambient , for industrial ambient temperature. minimum value: ?40 c. maximum value: +85 c on page 50, in the heading ?dc characteristics over commercial operating ranges,? change ?commercial? to ?commercial and industrial.? on page 56, in the section titled ?thermal charac- teristics,? change ?the lansc520 microcontroller is...? to ?lansc520 microcontroller commercial temperature devices are...? in the first sentence. on page 57, replace table 15 with the updated ver- sion reproduced below. this new table adds a new row for t case = 100 c. on page 59, in the heading ?switching characteris- tics over commercial operating ranges,? change ?commercial? to ?commercial and industrial.? valid combinations lansc520 ? 100 lansc520 ? 133 ac lansc520 ? 100 ai table 15. maximum t a for plastic bga package with 6-layer board 1 notes: 1. the board type is described in the jedec standards document entitled thermal test chip guide- line (wire bond type chip) at www.jedec.org. on the home page click on the link free standards and docs, and then click on the document link jesd51-4 under jedec publications. t case cpu clock rate airflow (linear feet per minute) 0 200 400 600 800 85 c 133 mhz 67.3 c69.8 c71.3 c72.2 c72.7 c 100 mhz 70.1 c72.2 c73.5 c74.3 c74.7 c 100 c 2 2. t case = 100 c data is for industrial temperature devices only. 100 mhz 85.1 c87.2 c88.5 c89.3 c89.7 c
2 lansc520 microcontroller datasheet amendment amendment trademarks amd, the amd logo, and combinations thereof, and lan are trademarks of advanced micro devices, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies. disclaimer the contents of this document are provided in connection with advanced micro devices, inc. ( ? amd ? ) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make c hanges to speci- fications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or oth erwise, to any in- tellectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, th e implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical impla nt into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's p roduct could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discont inue or make changes to its products at any time without notice.

▲Up To Search▲

Price & Availability of ELANSC520-100AC

	To Download ELANSC520-100AC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .